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Problem with TLV320AIC23B

Vasilis Kostelidis
Prodigy 50 points
Other Parts Discussed in Thread: TLV320AIC23B

I have problems with the TLV320AIC23B.

My digital output does not seem to produce correct audio samples. It is somehow arbitrary. I give a 1 kHz signal as an input. While the i2s is correct, meaning that the CLK, LRCOUT and DATA are correct with their timing, my DATA seems to be wrong.

When I measured the VMID voltage, in one chip, I found it to be almost zero, in another chip, almost as high as the AVDD and in another one, a little less than AVDD/2.

I assume that my board somehow "burns" the IC, but I have check everything, it is just the power supply and the input filter.

Can anyone suggests how is it possible to damage the chip in order to make the VMID not to work? Thanks.

  • 0
    TI__Mastermind 28585 points

    Vmid voltage will depend on programming. D0 in the power down register must be set to a 0 before any voltage will be seen. Are you certain that your control registers are correct? Are you looking at the ADC output or the DAC out? The number system is Binary Two's Complement.

  • 0 in reply to Converter Apps
    Prodigy 50 points

    Hello, thanks for the answer.

    Yes, I do set the values of the power down register to the values I want. For example, my DAC is not enabled, I just want the i2s. This is the value I am giving to the power down register, after reset: 0A.

    The voltage of VMID will depend on programming of the control registers? Can you explain this to me a bit more? What values will affect that? But again, since I am programming all the ICs with the same program, then I guess that indeed they have gone bad, else they should all give the same voltage.
    I know it is a signed two's complement number, but when I look at the I2S output, I can see positive and negative values randomly, whereas, all the negative values should be together and all the positive together (I am giving a 1 kHz sine wave as an input). In the case of the IC where the VMID is zero, I can also see some audio data in I2S in the right channel, which is not enabled.
    Any idea, please contribute. I am burning here.
    P.S. Is it possible to make a mistake in the digital audio interface format? It has a bit called LRSSWAP and another one, LRP which, I don't exactly understand what they are doing. I have the value 42, that is, DAC left/right swap is disabled and right channel on, LRCIN high.
  • 0 in reply to Vasilis Kostelidis
    TI__Mastermind 28585 points

    LRSWAP will put the left channel data on the right channel space and the right channel data on the left channel space. LRP determines whether the Left channel will come when LRCK is high or low (if you change them both, you would be back where you started). 

     

    If you can send your schematic and register settings, i will be happy to take a look. I have seen cases where the I2C commands weren't robust which would cause intermittent behavior. It could also be damaged parts.

  • 0 in reply to Converter Apps
    Prodigy 50 points

    I think that if the schematic had something wrong, then the IC would not respond to my commands, or as you say, perhaps it is the SPI.

    These are my register settings:

    spi_send(0x1E00);

    spi_send(0x1E00);

    spi_send(0x1E00);

    spi_send(0x1E00); //reset four times.

    for(i = 0; i < 0x1fffff; i ++); //small delay.

    spi_send(0x0C0A); //power down, enabled: device power, clock, oscillator, outputs (is this needed?), ADC, LINE.

    spi_send(0x0017); //left line input, disable simultaneous volume/mute, normal, 101111 db

    spi_send(0x0280); //right line input, disable simultaneous volume/mute, muted

    spi_send(0x0400); //left channel headphone, simultaneous update disabled, zero cross detect off, 0 db

    spi_send(0x0600); //right channel headphone, simultaneous update disabled, zero cross detect off, 0 db

    spi_send(0x0E42); //digital audio interface, master mode, LRSWAP disabled, right channel on, LRCIN high, 16 bit, I2S

    spi_send(0x0A0A); //digital audio path, DAC soft mute enabled (I don't want DAC), de-emphasis control 32 kHz, ADC high pass filter enabled

    spi_send(0x1018);//sample rate, clock input divider MCLK, clock output divider MCLK, 32 kHz with 12,288 MHz, normal mode

    spi_send(0x0802); //analog audio path, sidetone disabled, DAC off, bypass disabled, line select LINE, microphone muted

    spi_send(0x1201); //digital interface activation.

     

    I don't know how to post images, can you tell me how?

    Thanks a million!!!

  • 0 in reply to Vasilis Kostelidis
    Prodigy 50 points

    Oh sorry, I am so stressed I didn't even see it. The first image is without the grounds (I don't know how to see the ground in eagle) and the second image with the ground, but you cannot see the pcb clearly.

    6076.board1.TIF

    4810.board2.TIF

    And the register settings are above.

     

    Thanks again.