Hi team,
I am trying to utilize Beep generation function of TLV320DAC3100-Q1.
The only clock I supply to this chip is MCLK, but I found the other e2e thread explaining that the Beep generation function requires
at least 8 clock cycles of bclk to initialize internal logic.
- Could you advise which register to set to enable bclk?
setting page 0 register 27 D3 to 1 is enough?
register 29 and 30 also need to be set?
- Does the frequency of bclk matter for this purpose? (any divide ratio is OK?)
regards,