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TLV320DAC3100-Q1: how to enable bclk for beep generation

Part Number: TLV320DAC3100-Q1

Hi team,

I am trying to utilize Beep generation function of TLV320DAC3100-Q1.

The only clock I supply to this chip is MCLK, but I found the other e2e thread explaining that the Beep generation function requires

at least 8 clock cycles of bclk to initialize internal logic.

- Could you advise which register to set to enable bclk?

setting page 0 register 27 D3 to 1 is enough?

register 29 and 30 also need to be set?

- Does the frequency of bclk matter for this purpose? (any divide ratio is OK?)

regards,

  • Hi, Shinji,

    Yes, this is correct. In order to enable the beep generator from the processing blocks, it is necessary of few BCLK pulses (around 8 pulses as you mentioned) to get the generator initialized. So, if you only have MCLK as input clock, you would require to set the TLV320DAC3100-Q1 in master mode. In this way, the BCLK can be generated by the device.

    This is the suggested configuration for the BCLK generation. The BCLK frequency doesn't matter in this case, so you may configure the BCLK N-val divider as you prefer.

    Page 0 / Register 27 / Bit D3 = 1
    Page 0 / Register 29 / Bit D2 = 1 (optional, if this bit is not configured, the BCLK will be enabled until the DAC blocks are powered up)
    Page 0 / Register 30 / Bit D7 = 1 (Bits D6-D0 optional)

    The BCLK generation requires of a DAC_CLK or DAC_MOD_CLK to work. So, you must ensure that NDAC (page 0 / register 11) and MDAC (page 0 / register 12) are enabled to get the BCLK working.

    I hope this helps you. Please let me know if you need additional support on this.

    Best regards,
    Luis Fernando Rodríguez S.