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TLV320ADC3101: Best way to put this part into low power mode when not in use?

Robert Koch44
Prodigy 190 points
Part Number: TLV320ADC3101


I'm trying to figure out the best way to put the TLV320ADC3101 into a low power state when it's not in use. Page 14 of SLAS553B has a section titled "Software Power Down" which states the following:

By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit
block can be controlled by writing to the appropriate control register. This approach allows the lowest power supply
current for the functionality required. However, when a block is powered down, all of the register settings
are maintained as long as power is still being applied to the device.

I've read this section several times and cant figure out exactly what it's trying to say, and this is the only section in the document that mentions the Software Power Down feature. Is it suggesting that the method of performing a software power down is to apply a reset? The section goes on to mention that all register settings are maintained as long as power is still applied. So after a reset condition the registers are still maintained as they were previously programmed by the user?

If someone can explain this in more detail I'd be very grateful

Thanks,

Rob

  • 0
    TI__Mastermind 30220 points

    Rob, 

    Its saying that the default state of the device after reset is to have the ADC powered down, the PGAs are muted and powered down, the PLL is off, Clock dividers off, DSP off etc...  and when you power the device or reset the device it will need to be configured (or reconfigured).  So there is no self configuration of the device. the device does not retain configurations after a reset

    Holding reset low is the best way to maintain low power, but the second best way would be to have the device configured, but all of the internal blocks (ADCs, DSPs, PLL etc...) powered down.  With the device configured, it takes very few commands to get the device completely up and running

    best regards

    -Steve wilson

  • 0 in reply to Steve-Wilson
    Prodigy 190 points

    Hi Steve,

    Thanks for your reply. I've been trying to put the device into low power mode by powering down the internal blocks. I'm not noticing any reduction in power however. The blocks I'm powering off are the following:

    PLL Power Off - Page 0, Register 5

    BCLK N Divider off - Page 0, Register 30

    MICBIAS powered off - Page 1, Register 51

    ADC Input powered off - Page 0, Register 81

    NADC Clock divider powered off - Page 0, Register 18

    MADC Clock divider powered off - Page 0, Register 19

    I notice very little change in power when I update the above registers. The only setting that seems to have any effect is when I turn off the microphone bias voltage. I'm able to configure the ADC in it's runtime configuration just fine.

    My microcontroller serves as the master of the audio bus for my application, and it generates the word clock, bit clock and master clock. The audio bus and master clock is disabled when both setting up the runtime configuration and powering the above listed internal blocks down. Is it a requirement that the audio bus master clock be left running when powering the blocks off?

    Thanks again,

    Rob

  • 0 in reply to Robert Koch44
    TI__Mastermind 30220 points

    Robert, 

    All of those blocks will be powered off by default.  you won't really see much change powering down the clock dividers.  I would still expect some change with the PLL or ADC 

    What kind of current draw/power consumption are you seeing?

    best regards,

    -Steve wilson