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TLV320AIC3111: Clock configuration help required.

Souvik Saha
Intellectual 625 points

Part Number: TLV320AIC3111

Hello,

I'm facing problems with setting the clock frequencies on my device. I need a sampling frequency of 44.1kHz
As per my understanding, the MODEVM interface is giving a 11.2896 MHz as MCLK, PLL_CLK of around 90MHz and the internal clock dividers step the sampling frequency to 44.1 kHz.

For my application, I'm supplying a 4.096MHz signal to the MCLK from a microcontroller

The configurations I'm supplying is as follows - 

R = 1, J = 22, D = 06, P = 1

By my calculations, this will give PLL_CLK of 90.3618 MHz, which is similar to the PLL_CLK as the EVM example. Do I need to change the other values such as MADC, NADC, AOSR etc? As the PLL_CLKIN is same, it shouldn't make any difference for the rest of the clock dividers right? I tried this approach but I've had no luck in obtaining filtered output. What am I missing out on?

I can PM the ProcessFlow and the code I've written if required.

Regards,

Souvik

  • 0
    TI__Mastermind 30250 points

    Souvik, 

    Not sure how you generated your PLL values there. 

    But if your MCLK is already a multiple of your Fs,  you don't need a D value. 

    I would suggest trying values of

    P=1

    R=1

    J=24

    D=0000

    N= 4

    M=12

    This is a good place to start.  The DSP clock max is in the Datasheet,  but you can change the M/N ratio so that the DSP clock is higher if necessary. 

    best regards

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Intellectual 625 points

    Thanks Steve.

    While editing the SystemConfiguration on PurePath Studio, I find two different locations where  P, R, J D, N, M are changed. One of them is at the top of the predefined code as

    reg[0][4] = 0x03 ; PLL_CLKIN = MCLK = 11.2896 MHz., CODEC_CLKIN=PLL_CLK
    reg[0][5] = 0x91 ; PLL Power Up, P = 1, R = 1
    reg[0][6] = 0x08 ; J = 8
    reg[0][7] = 0x00 ; D(13:8) = 0
    reg[0][8] = 0x00 ; D(7:0) = 0 (CODEC_CLKIN = (PLL_CLKIN * R * J.D) / P = 90.3168 MHz.

    The other one is

    %%if (%%prop(SampleRate) == 16000)
    reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24
    reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24
    reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
    reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
    reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
    reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB)
    reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB)
    reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
    reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on
    reg[ 0][ 20] = 0x80 ; AOSR = 128
    reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
    %%endif

    Which of these blocks do I change?

    What other changes must I do to make the clock source as per my requirements?

  • 0 in reply to Souvik Saha
    TI__Mastermind 30250 points

    Souvik, 

    You must click on the AIC3254 framework and in the properties menu click on the SystemSettingsCode.  then click on the little box with the ... 

    This will open up your device configuration.  The Clock settings for 16khz are already similar to what I've posted, only with a larger M_ADC value and lower N_ADC value.  same clock values of course. 

    the DAC has a DOSR of 384 ,so the M value is lower, but the clocks are the same. 

    What are you trying to accomplish here?

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Intellectual 625 points

    I'm trying to generate the necessary clock signals with the controller I'm using. The signal I'm giving is 4.096Mhz.

  • 0 in reply to Souvik Saha
    TI__Mastermind 30250 points

    Souvik, 

    do you want the Codec to generate the BCLK and WCLK?  

    -Steve 

  • 0 in reply to Steve-Wilson
    Intellectual 625 points

    Not for our current application, but we might need it in future versions.

  • 0 in reply to Souvik Saha
    TI__Mastermind 30250 points

    Souvik, 

    So you are providing a 4.096Mhz MCLK, and you are using those PLL configuration settings and it works on the EVM but not on your board?  

    Are you sure you're actually writing the registers?  

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Intellectual 625 points

    Hey Steve.

    I figured out the issue. According to this link below, after writing to the PLL register and turning it on, we need to give a 10ms delay, for the PLL to lock. 

    https://e2e.ti.com/support/audio/f/6/p/773092/2859069?tisearch=e2e-sitesearch&keymatch=%2525255BFAQ%2525255D%25252520TLV320AIC%25252520CODECs#2859069 

    I added it into my code as below

    { 4,0x03},
    // # reg[0][5] = 0x91 ; PLL Power Up, P = 1, R = 1
    {254,10},

    and that seemed to do the trick. The audio quality seems amplified and filtered. I'll need to test the output once to verify if it's obeying the filter characteristics I've set.
    Thanks for your help!