Hello.
I would like my TLV320AIC3100 audio codec to receive audio data through I2S interface and play audio on speaker. Codec's registers are in my case configured by FPGA via I2C and also audio data is sent from same FPGA via I2S protocol. The problem that I have is that there is no audio output on speaker. I assume I forgot to configure some register or configured it wrongly.
My questions:
- Is there a specific order in which registers have to be configured (written to)?
- Can someone provide me complete register settings for my case (audio data in via I2S and out on speaker) or finds mistakes in my configuration (listed below)?
My settings and register values are listed below:
- I2S protocol:
- mclk = 6.4 MHz
- bclk = 1.6 MHz
- (sampling frequency) fs = 50 kHz = wclk (word clock)
- Configuration of registers (in order that registers are being written to):
- page 0 ----------------------
- reg 4 : 0x03 (pll_clkin = MCLK, codec_clkin = PLL_CLK)
- reg 5 : 0xA1 (P=2, R=1, pll powered up)
- reg 6 : 0x1D (J=29)
- reg 7 : 0x00 (D = 0)
- reg 8 : 0x00 (D = 0)
- reg 11 : 0x84 (NDAC = 4, ndac power up)
- reg 12 : 0x84 (MDAC = 4, mdac power up)
- reg 13 : 0x00 (DOSR msb = 0)
- reg 14 : 0x74 (DOSR lsb = 116)
- reg 27 : 0x00 (i2s protocol, 16 bits, BCLK = input, WCLK = input)
- reg 53 : 0x10 (Dout disabled)
- reg 63 : 0xF2 (L&R ch DAC power up, R ch datapath = off, soft stepping disabled)
- reg 64 : 0x02 (L&R DAC not muted, R DAC volume same as L)
- reg 65 : 0x0F (volume = 7.5 dB)
- reg 116 : 0x00 (DAC volume controlled by register)
- page 1 -----------------------------------------------------------
- reg 32 : 0x06 (speaker off) <--- I turn speaker ON separately when I need the sound to be displayed, every other time it is turned OFF.
- reg 35 : 0x40 (L DAC routed to mixer)
- reg 38 : 0x80 (L ch analog volume control routed to mono class-D output driver)
- reg 42 : 0x0C (mono class-D driver not muted, gain = 12dB)
- page 3 ------------------------------------------------------------
- reg 16 : 0x06 (divider is 6 to generate apx. 1MHz clock as desired by datasheet)
