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Original question:

TLV320AIC3101: Set Fsref to 8k or 16k

TLV320AIC3101: Set to Lower Fs than 5kHz

Takashi Onawa
Genius 13200 points
Part Number: TLV320AIC3101


Hi Team,

My customer wants to set lower sampling rate like 5khz.

Are there any way to set a lower Fs than 5kHz to TLV320AIC3101? 

Regards,

Takashi Onawa

  • 0
    TI__Mastermind 22950 points

    Hello Takashi,

    Section 11.3.3 of the data sheet explains the different sample rates you can achieve and how to achieve them. 

    As an example, if Fs(ref) = 44.1kHz, then the smallest sample rate you can achieve is Fs(ref)/6. That would equate to roughly 7.35 kHz. You can choose the sample rates by modifying register 2. 

    Note that the DAC sampling rate needs to be equal to the sample rate of the ADC. I hope this helps!

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    TI__Genius 13200 points

    Hi Aaron-san,

    Sorry for my slow response on this.

    OK, I understood the min fs is 7.35Hz. And it's restricted by fs divider setting on register 2.

    Do you think it is possible to get 5ksps data by using  MCLK * 0.68(5k / 7.35k) clock?

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Mastermind 22950 points

    Hello Takashi-san,

    A Fs below Fs(ref)/6 is not supported. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    TI__Genius 13200 points

    Hi Aaron-san,

    But MCLK supports 512kHz to 50MHz input right?

    "The part can accept an MCLK input from 512 kHz to 50 MHz"

    Could you tell me what you concern to use lower and higher Fs on our Cordec?

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Mastermind 22950 points

    Hello Takashi-san,

    We are actively looking into this. 

    Can you tell me if the customer is using the PLL? If so, then the minimum Fs(ref) is 39kHz. When divided by 6, you can achieve a sampling rate of 6.5kHz.

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    TI__Genius 13200 points

    Hi Aaron-san,

    Thanks for your comment.

    MCLK  will be controlled by external PLL and they just want to get I2S format data sampled by specific Fs rate, less than 5kHz.
    They don't plan to use internal PLL, CLKDIV line will be used with Q=2 setting.
    They just want to use this device as ADC with mic bias and they don't need to keep general audio sampling format in their app.
    Actually, their system has been working properly with the similar setting.

    Then, what is your concern in such the use case?
    Please let me know if there are any deterioration in characteristics.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Genius 13200 points

    Hi Aaron-san,

    Please tell me risk when the device is used in such the setup...
    Since current system have been working without any issues for long time, I need to explain why it is not recommended, in order to close this question.

    Regards,

    Takashi Onawa

  • 0 in reply to Takashi Onawa
    TI__Mastermind 22950 points

    Hello Takashi-san,

    Apologies for the delayed response. 

    I have confirmed with the design team that the minimum limitation of the codec is Fs(ref) = 39kHz which would allow a minimum sampling frequency of 6.5kHz. This is likely due to the minimum ADC modulator clock for which the analog design in done and simulated.

    Although this is a limitation, we are not sure if this is a hard or soft limitation. We are also not sure what kind of behavior the device may exhibit if pushed outside data sheet recommendation. 

    Regards,

    Aaron