TLV320ADC3101: Clock Configuration

Sadanori Kato

Hi,

The noise is output with PRB_R1 if using TLV320ADC3101 with the following clock settings.
So, could you please tell me the root cause and workaround ?

Best regards,
Kato

over 6 years ago

0 Steve-Wilson over 6 years ago

TI__Mastermind 30250 points

Kato-san,

Figure 28 in the datasheet contains a clock tree with a constraint in the lower Left corner:

In this case, your IADC is 188 while MADC x AOSR = 64.

MADC xAOSR must be greater or equal to IADC.

best regards,

-Steve Wilson

0 Sadanori Kato over 6 years ago in reply to Steve-Wilson

Guru 36540 points

Hi Steve-san,

Thank you for your prompt reply.

I understand and will contact you if I have additional questions from our customer.

Best regards,
Kato

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TLV320ADC3101: Clock Configuration