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SRC4382: Channel status and User data buffer maps

Jejomar Ildefonso
Genius 9650 points

Part Number: SRC4382

Hi Team,

Need your help on this. Our customer wants some clarification with the way the data and channel status buffer maps of the DIR and DIT were set in Tables 5-8 (Register Pages 1 and 2) of the datasheet. In here bit 0 is defined as the MSB. Opposite with the control registers' set-up having the bit 7 being the MSB.

For the first byte (byte 0), it is said the bit 0 defines the transmission mode. However we can't find further information why the MSB was set-up this way.

We'll highly appreciate your inputs.

Kind Regards,

Jejomar

  • 0
    TI__Mastermind 30230 points

    Jejomar, 

    Im afraid for a device this old, getting commentary from the original design team on why a decision was made one way or another is at best very unlikely,  but in this case I am certain that the design engineers for this project have retired, or left TI.  

    I can understand the customers frustration with this, but I'm afraid I cannot offer an reasoning to explain or alleviate. 

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    TI__Genius 9650 points

    Hello Steve,

    I understand. Thank you for looking into this. It is really not that we need the exact reason of this set-up, we just need to confirm if there has been a discrepancy within the datasheet.

    The question is, on table 5-8, are the bits marked "BIT 0" the MSBs (having a decimal value of 128), and the bits marked "BIT 7" truly the LSBs (having a decimal value of 1)?

    Kind Regards,

    Jejomar

  • 0 in reply to Jejomar Ildefonso
    TI__Genius 9650 points

    Hello Steve,

    May I request for a follow-up on this?


    Kind Regards,

    Jejomar

  • 0 in reply to Jejomar Ildefonso
    TI__Mastermind 30230 points

    Jejomar, 

    In the limited documentation I have I do not see any reason to not believe the datasheet.  Is the customer reading back data that doesn't make sense? or what appears to be the problem?

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    TI__Genius 9650 points

    Hello Steve,

    The customer just needs the clarifications since the arrangement of the register pages 1 & 2 were not the common arrangement where Bit 7 was usually being tagged as the MSB, which was the other way around on this case (Bit 0 is the MSB). At first glance they thought there was something erroneous since by their experience this was not the usual way the bits in a register were set.

    Kind Regards,

    Jejomar

  • 0 in reply to Jejomar Ildefonso
    TI__Mastermind 30230 points

    Jejomar, 

    As far as I can tell,  this is the way the designers intended it as the documentation I have shows it like this going back through early drafts of the Datasheet, and other design review documents. 

    Again, at this point we can only guess why the designers did it they way they did. 

    best regards,

    -Steve Wilson