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TLV320AIC3107EVM-K: BCLK or MCLK EVM Question

Lindsey Fike
Intellectual 2250 points
Part Number: TLV320AIC3107EVM-K


Posting for a customer- 

" 

I have the EVM wired up to our board and the I2C and I2S look good on the scope but it doesn’t play sound out a speaker or headset. I am using the EVM without the USB expansion board. Intel seems to believe that it requires a Master Clock signal from the CPU for the codec to function. From the following diagram from the datasheet, I assume you can use either a bit clock or a master clock for the I2S bus.

Can you confirm it can use the Bit Clock(BCLK) or does it require a master clock(MCLK)? Is there a register I need to set in order to choose which clock the system should use? 

Thanks!

  • 0
    TI__Guru 64205 points

    Hello,

    When using the EVM with the USB-MOD-EVM controller we operate the device in 4-wire mode.  However, as you've noted the PLL can be used to convert the BCLK input into a valid internal MCLK.  This is confirmed in the datasheet text below the image you've attached:

    The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK input can also be used to generate the internal audio master clock.

  • 0 in reply to Collin Wells
    TI__Intellectual 2250 points

    Do you know if this is a register I can set in the machine driver or do I need to modify the codec driver?

    Do you need to see the Machine Driver for the Intel Reference board?

  • 0 in reply to Lindsey Fike
    TI__Guru 64205 points

    Hello,

    There are many driver implementations out there for these devices and we're not going to know what has/hasn't been implemented in the one you're using.  You'll need to review the driver code and determine if dedicated functions have been created to adjust those register values and if not you'll need to either create them or use generic I2C read/write commands to achieve them.

  • 0 in reply to Collin Wells
    TI__Intellectual 2250 points

    Can you please confirm the register (Table 109. Page 0 / Register 102: RESET VALUE Clock Generation Control Register from the Datasheet) is the correct register that sets the internal clock from MCLK to BCLK?

    Are there other registers I need to be concerned with changing to get the codec working?

    I get I2C ACKs back when I set parameters in the ALSA mixer so I believe the chip is powered and working but I need it to use the BCLK and not the MCLK.

  • 0 in reply to Lindsey Fike
    TI__Mastermind 22950 points

    Hello Lindsey,

    Yes, Register 102 will allow the user to select either MCLK or BCLK as CLKDIV or PLL_CLKIN. You want to also make sure that the CODEC_CLKIN source is correct. This is determined in register 101.

    As for your other question regarding what other registers need to be set, this is of course determined by what path the customer is taking and what blocks need to be powered on. A good starting point is to make sure that the DAC and output blocks being used are powered on as well as the correct output path is enabled. 

    Regards,

    Aaron

  • 0 in reply to Lindsey Fike
    TI__Mastermind 30220 points

    Lindsey, 

    The reset value for register 102 is correct,  however if you are not providing any input to the MCLK pin,  You need to also assign the BCLK to the CLK_DIV input (even if you are not using it)

    So register 102 would need to be configured as 0xA2

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    TI__Intellectual 2250 points

    I’ve found this in the codecs/tlv320aic3x.c codec driver file:

                   static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,

                                    int clk_id, unsigned int freq, int dir)

    {

            struct snd_soc_codec *codec = codec_dai->codec;

            struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);

     

            /* set clock on MCLK or GPIO2 or BCLK */

            snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,

                                    clk_id << PLLCLK_IN_SHIFT);

            snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,

                                    clk_id << CLKDIV_IN_SHIFT);

     

            aic3x->sysclk = freq;

            return 0;

    }

    I believe this is where I need to get the call to set the system to use the BCLK clock but I am not sure which values set it to MCLK GPIO2 or BCLK

     

    The call down to this function sends a 0 as a parameter which would be the clk_id. Is it as simple as 0 1 2?

     Can you confirm this is correct? 

  • 0 in reply to Lindsey Fike
    TI__Mastermind 22950 points

    Hello Lindsey,

    Unfortunately, I am unfamiliar with the driver and do not have an answer for you. Perhaps there is an example online that will help.

    Regards,

    Aaron

  • 0 in reply to Lindsey Fike
    TI__Mastermind 30220 points

    Lindsey,

    If you look in the TLV320AIC3x.h file, you will see that three constants are created on lines 202-204. use these.

    Note that there is an option for GPIO2,  which the AIC3107 does not have.  This driver is used for the entire AIC310x and AIC33 family,  and so the AIC3106 and AIC33 which both have two GPIOs can use that option while all other AIC310x or AIC3x devices cannot.

    best regards,

    -Steve wilson