Porting AEC algorithm to a custom board.

Hi Javier Martin,

IDAC value has to be lessthan or equal to MDAC*DOSR and IADC value has to be lessthan or equal to MADC*AOSR. Derived clocks have to stay within the Maximum ratings specified in the datasheet.
I modified PLL,Divider,BDIV_CLKIN values.

Here is the script with modifications. Let me know if it helps.

#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][1]=0x01
> 01
#
w 30 15 03
#
> 88
#
### ----------- Removed miniDSP stuff
#
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][61] = 0x00                ; ADC programmable mode selected (remove as miniDSP is not being used)
### w 30 3d 00
#
w 30 0f 18
#
> 00
#
### ----------- Removed miniDSP stuff
#
#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][1 ] = 0x08     ; reg(1)(0x01 => 1 )     Crude avdd disabled
> 08
#     # reg[1][2 ] = 0x01     ; reg(1)(0x02 => 2 )     AVDD LDO power up
> 01
#     # reg[1][10] = 0x03     ;  LDOIN 1,8-3,6V
w 30 0A 03
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][60] = 0x00     ; DAC programmable mode selected (remove as miniDSP is not being used)
### w 30 3c 00
#     # reg[0][04] = 0x03     ; PLL_clkin = MCLK,codec_clkin = PLL_CLK
w 30 04 03
#     # reg[0][05] = 0xD1     ; PLL Power up, P = 5, R = 1
> D1
#     # reg[0][06] = 0x13     ; J = 19; 80 MHz <= PLL_CLK <= 110 MHz; PLL_CLK = (19.6608/5 * 25MHz) = 98.304MHz
> 13
#     # reg[0][07] = 0x19     ; D = 6608, D(13:8) = 0x19
> 19
#     # reg[0][08] = 0xD0     ; D(7:0) = 0xD0
> D0
#     # reg[0][11] = 0x82     ; NDAC is powered up and set to 2
w 30 0b 82
#     # reg[0][12] = 0x88     ; MDAC is powered up and set to 8
> 88
#     # reg[0][13] = 0x03     ; DOSR = 768, DOSR(9:8) = 0
> 03
#     # reg[0][14] = 0x00     ; DOSR(7:0) = 768
> 00
#     # reg[0][29] = 0x01     ; bdiv_clkin = dac_mod_clk
w 30 1d 01
#     # reg[0][30] = 0x8c     ; blk_N = 12
w 30 1e 8c
#     # reg[0][18] = 0x88      --powerup NADC and value is 8
w 30 12 88
#     # reg[0][19] = 0x8C      --Powerup MADC and value is 12
> 8C
#     # reg[0][20] = 0x40      --AOSR is 128
> 80
#     # reg[0][23] = 0x04     ; ADC Decimation ratio = 4
w 30 17 04
#     # reg[0][17] = 0x04     ; DAC Interpolation ratio = 4
w 30 11 04
#     # reg[0][27] = 0x4c     ; mode is dsp,wordlength is 16, codec is bclk and wclk master
w 30 1b 4c
#     # reg[0][63] = 0xd6     ;11010110b     ; POWERUP DAC left and right channels (soft step disable)
w 30 3f d6
#     # reg[0][81] = 0xc2     ;11000010b     ; -- POWERUP ADC left and left channel (soft step disable)
w 30 51 c2
#     # reg[0][82] = 0x00     ;00000000b     ; -- unmute ADC
> 00
#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][51] = 0x68     ; reg(1)(0x33 => 51)*    ADC Enable Mic Bias
w 30 33 68
#     # reg[1][52] = 0x04     ; reg(1)(0x34 => 52)*    ADC IN3_L is selected for left P
> 04
#     # reg[1][54] = 0x40     ; reg(1)(0x36 => 54)     ADC CM1 is selected for left M
w 30 36 40
#     # reg[1][55] = 0x04     ; reg(1)(0x37 => 55)*    ADC IN3_R is selected for right P
> 04
#     # reg[1][57] = 0x40     ; reg(1)(0x39 => 57)     ADC CM1 is selected for right M
w 30 39 40
#     # reg[1][59] = 0x3C     ; 0x3C reg(1)(0x3b => 59)     ADC unmute left mic PGA (+30 dB)
w 30 3b 3c
#     # reg[1][60] = 0x3C     ; reg(1)(0x3c => 60)          ADC unmute right mic PGA (+30 dB)
> 3c
#     # reg[1][71] = 0x30     ; reg(1)(0x47 => 71)     Quick Mic-PGA Power-up
w 30 47 30
#     # reg[1][20] = 0x35     ; De-pop,^RC,5K, 47uF
w 30 14 35
#     # reg[1][12] = 0x08     ; reg(1)(0x0c => 12)     DAC LDAC AFIR routed to HPL
w 30 0c 08
#     # reg[1][13] = 0x08     ; reg(1)(0x0d => 13)     DAC RDAC AFIR routed to HPR
> 08
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][64] = 0x00     ; reg(0)(0x40 => 64)     DAC Left and Right DAC unmuted with indep.  vol. ctrl
w 30 40 00
#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][16] = 0x00     ; reg(1)(0x10 => 16)     DAC HPL unmuted with 0dB gain
w 30 10 00
#     # reg[1][17] = 0x00     ; reg(1)(0x11 => 17)     DAC HPR unmuted with 0dB gain
> 00
#     # reg[1][9 ] = 0x30     ; reg(1)(0x09 => 9 )     DAC Power up HPL and HPR driver
w 30 09 30
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][68] = 0x0f ; Switch off H/W DRC
w 30 44 0f
#     --------------------------------------------------------------- page 8 is selected
w 30 00 08
#     # reg[8][1] = 0x04    ; adaptive mode for ADC (disabled as miniDSP not used)
### > 04

#############################################################
#                       Select Page 1
w 30 00 01
#                      Turn On Mic Bias generated from LDOIN
w 30 33 68
### d 30

###############  IN 3 SET UP START *************************
#
#                      IN2_L is selected for left P 10k
w 30 34 10
#
#                      IN2_R is selected for left M 10k
w 30 36 10
#
#                      IN1_R is selected for right P 10k
w 30 37 40
#
#                      IN1_L is selected for right M 10k
w 30 39 10
#
###############  IN 3 SET UP END ****************************

#                      unmute left mic PGA
w 30 3b 48
#                      unmute right mic PGA
w 30 3c 00
#**********  ENABLE DAC and HP OUTPUTS *********************
w 30 00 01

#########################################################

#                      Power up LOL and LOR driver
w 30 09 0c
#                      LDAC AFIR routed to LOL
w 30 0e 08
#                      RDAC AFIR routed to LOR
w 30 0f 08
#                      LOL unmuted with 0dB gain
w 30 12 00
#                      LOR unmuted with 0dB gain
w 30 13 00
#                      Page 0 selected
w 30 00 00
#                      L&R DAC powerup Ldata-LDAC Rdata-RDAC
w 30 3f d6
#                      DAC left digital PGA
w 30 41 00

#                      Left and Right DAC unmuted with indep.  vol. ctrl
w 30 40 00

Thank you for tunning the file for me.

With the .cfg you provided I can record and play audio flawlessly. Even some noises I had with my first .cfg file have disappeared and the audio quality is much better.

However, when I add miniDSP AEC  algorithm to your .cfg file (see attached file), I can only record audio but playback doesn't work. This algorithm has been tested OK with EVM USB board.

8422.ti_support_dsp_nothing.txt

Hi Javier Martin,

There is one typo in my previous posting. I will correct that posting.

Correction:

 IDAC value has to be less than or equal to MDAC*DOSR

and IADC value has to be less than or equal to MADC*AOSR

I will try looking at the your script today.

Hi, we are still stuck with this problem

The script has been reviewed several times but, unless there is a problem with binary code for the miniDSP regarding our audio path configuration we don't see how it makes playback not to work when miniDSP code is added.

Have you found anything? If AEC algorithm cannot run in our custom board we will have to choose another audio codec.

Regards.

Hi Javier Martin,

I did not find any issues with analog settings in your script. However, When I load the .cfg file, I heard noise on the output. Can you please send the Process flow that you are using? What is the version of PPS being used?

Have you refered the document "C:\Program Files\Texas Instruments Inc\PurePath Studio Portable Audio\ApplicationNotes\AIC3254 Acoustic Echo Cancellation Application Note.pdf"

Regards,

PPS version I am using is "version 4.80 build 1 revision 10211".

You will find my process flow attached.

3513.AIC3254_AEC_32_1.zip

I am currently following the application note you mentioned in your previous post, more precisely I am at step 4-a (page 18). Although the whole tuning process has already been tested for EVM board we are starting now from the beginning for our custom board.

The script I sent before is a combination of the one generated by this PPS flow and audio patch and lock changes necessary to work on our custom board. As you know, as soon as miniDSP code is enabled playback stops working (record does work though).

Thank you.

Hi,

I moved to "version 4.80 build 1 revision 10211". I compared the script geranated based on the process flow that you sent. instructions and coeffcients match.

register settings differ as you mentioned in your email. I have two questions.

I2S mode is set to DSP Mode. Is this intended?

How is this script loaded in your system? Is it I2C? what speed?

If I change the settings from DSP to I2S, (and correct the PLL settings for EVM) playback is working fine on my evm.

Can you check a simple process flow on your system with just two components 1) InputOutput->MonoI2S_In and 2) InputOutput->MonoInt4xInt? This is to check playback.

Regards,

Mohan Yenigalla said:

I2S mode is set to DSP Mode. Is this intended?

Yes, our audio interface is working in DSP mode instead of I2S.

Mohan Yenigalla said:

How is this script loaded in your system? Is it I2C? what speed?

It is loaded using I2C at 100KHz, written values are read back and checked.

Mohan Yenigalla said:

Can you check a simple process flow on your system with just two components 1) InputOutput->MonoI2S_In and 2) InputOutput->MonoInt4xInt? This is to check playback.

The first script at the beginning, the one you made a fix on, has been tested in our custom board and both record and playback work fine. The problem is when I enable miniDSP with the process flow and script you have available, you can easily tell the differences between both files with a diff command.

To make it more clear, here you have both files attached again:

1. Complete script with AEC algorithm generated with the process flow attached previously. Only record works, playback doesn't.

6332.ti_support_dsp_nothing.txt

2. Script with AEC algorithm removed and miniDSP disabled in ADC/DAC. Both record and playback work.

#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][1]=0x01
> 01
#
w 30 15 03
#
> 88
#
### ----------- Removed miniDSP stuff
#
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][61] = 0x00                ; ADC programmable mode selected (remove as miniDSP is not being used)
### w 30 3d 00
#
w 30 0f 18
#
> 00
#
### ----------- Removed miniDSP stuff
#
#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][1 ] = 0x08     ; reg(1)(0x01 => 1 )     Crude avdd disabled
> 08
#     # reg[1][2 ] = 0x01     ; reg(1)(0x02 => 2 )     AVDD LDO power up
> 01
#     # reg[1][10] = 0x03     ;  LDOIN 1,8-3,6V
w 30 0A 03
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][60] = 0x00     ; DAC programmable mode selected (remove as miniDSP is not being used)
### w 30 3c 00
#     # reg[0][04] = 0x03     ; PLL_clkin = MCLK,codec_clkin = PLL_CLK
w 30 04 03
#     # reg[0][05] = 0xD1     ; PLL Power up, P = 5, R = 1
> D1
#     # reg[0][06] = 0x13     ; J = 19; 80 MHz <= PLL_CLK <= 110 MHz; PLL_CLK = (19.6608/5 * 25MHz) = 98.304MHz
> 13
#     # reg[0][07] = 0x19     ; D = 6608, D(13:8) = 0x19
> 19
#     # reg[0][08] = 0xD0     ; D(7:0) = 0xD0
> D0
#     # reg[0][11] = 0x82     ; NDAC is powered up and set to 2
w 30 0b 82
#     # reg[0][12] = 0x88     ; MDAC is powered up and set to 8
> 88
#     # reg[0][13] = 0x03     ; DOSR = 768, DOSR(9:8) = 0
> 03
#     # reg[0][14] = 0x00     ; DOSR(7:0) = 768
> 00
#     # reg[0][29] = 0x01     ; bdiv_clkin = dac_mod_clk
w 30 1d 01
#     # reg[0][30] = 0x8c     ; blk_N = 12
w 30 1e 8c
#     # reg[0][18] = 0x88      --powerup NADC and value is 8
w 30 12 88
#     # reg[0][19] = 0x8C      --Powerup MADC and value is 12
> 8C
#     # reg[0][20] = 0x40      --AOSR is 128
> 80
#     # reg[0][23] = 0x04     ; ADC Decimation ratio = 4
w 30 17 04
#     # reg[0][17] = 0x04     ; DAC Interpolation ratio = 4
w 30 11 04
#     # reg[0][27] = 0x4c     ; mode is dsp,wordlength is 16, codec is bclk and wclk master
w 30 1b 4c
#     # reg[0][63] = 0xd6     ;11010110b     ; POWERUP DAC left and right channels (soft step disable)
w 30 3f d6
#     # reg[0][81] = 0xc2     ;11000010b     ; -- POWERUP ADC left and left channel (soft step disable)
w 30 51 c2
#     # reg[0][82] = 0x00     ;00000000b     ; -- unmute ADC
> 00
#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][51] = 0x68     ; reg(1)(0x33 => 51)*    ADC Enable Mic Bias
w 30 33 68
#     # reg[1][52] = 0x04     ; reg(1)(0x34 => 52)*    ADC IN3_L is selected for left P
> 04
#     # reg[1][54] = 0x40     ; reg(1)(0x36 => 54)     ADC CM1 is selected for left M
w 30 36 40
#     # reg[1][55] = 0x04     ; reg(1)(0x37 => 55)*    ADC IN3_R is selected for right P
> 04
#     # reg[1][57] = 0x40     ; reg(1)(0x39 => 57)     ADC CM1 is selected for right M
w 30 39 40
#     # reg[1][59] = 0x3C     ; 0x3C reg(1)(0x3b => 59)     ADC unmute left mic PGA (+30 dB)
w 30 3b 3c
#     # reg[1][60] = 0x3C     ; reg(1)(0x3c => 60)          ADC unmute right mic PGA (+30 dB)
> 3c
#     # reg[1][71] = 0x30     ; reg(1)(0x47 => 71)     Quick Mic-PGA Power-up
w 30 47 30
#     # reg[1][20] = 0x35     ; De-pop,^RC,5K, 47uF
w 30 14 35
#     # reg[1][12] = 0x08     ; reg(1)(0x0c => 12)     DAC LDAC AFIR routed to HPL
w 30 0c 08
#     # reg[1][13] = 0x08     ; reg(1)(0x0d => 13)     DAC RDAC AFIR routed to HPR
> 08
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][64] = 0x00     ; reg(0)(0x40 => 64)     DAC Left and Right DAC unmuted with indep.  vol. ctrl
w 30 40 00
#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][16] = 0x00     ; reg(1)(0x10 => 16)     DAC HPL unmuted with 0dB gain
w 30 10 00
#     # reg[1][17] = 0x00     ; reg(1)(0x11 => 17)     DAC HPR unmuted with 0dB gain
> 00
#     # reg[1][9 ] = 0x30     ; reg(1)(0x09 => 9 )     DAC Power up HPL and HPR driver
w 30 09 30
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][68] = 0x0f ; Switch off H/W DRC
w 30 44 0f
#     --------------------------------------------------------------- page 8 is selected
w 30 00 08
#     # reg[8][1] = 0x04    ; adaptive mode for ADC (disabled as miniDSP not used)
### > 04



#############################################################
#                       Select Page 1
w 30 00 01
#                      Turn On Mic Bias generated from LDOIN
w 30 33 68
### d 30


###############  IN 3 SET UP START *************************
#
#                      IN2_L is selected for left P 10k
w 30 34 10
#
#                      IN2_R is selected for left M 10k
w 30 36 10
#
#                      IN1_R is selected for right P 10k
w 30 37 40
#
#                      IN1_L is selected for right M 10k
w 30 39 10
#
###############  IN 3 SET UP END ****************************

#                      unmute left mic PGA
w 30 3b 48
#                      unmute right mic PGA
w 30 3c 00
#**********  ENABLE DAC and HP OUTPUTS *********************
w 30 00 01

#########################################################

#                      Power up LOL and LOR driver
w 30 09 0c
#                      LDAC AFIR routed to LOL
w 30 0e 08
#                      RDAC AFIR routed to LOR
w 30 0f 08
#                      LOL unmuted with 0dB gain
w 30 12 00
#                      LOR unmuted with 0dB gain
w 30 13 00
#                      Page 0 selected
w 30 00 00
#                      L&R DAC powerup Ldata-LDAC Rdata-RDAC
w 30 3f d6
#                      DAC left digital PGA
w 30 41 00

#                      Left and Right DAC unmuted with indep.  vol. ctrl
w 30 40 00

Regards.

Hi Javier Martin,

I tried the script you mentioned above in 1. it is working on my EVM if I change the PLL settings (based on EVM MCLK) and make Audio Interface to I2S and I2S Master. I am not sure about the reason why it is not working on your system. So, for debugging, I suggest to make a simple (I2S->Interpolator) processflow and check if the playback works with miniDSP enabled.

Regards,

Ok, I have tried with another process flow. You'll find it attached:

7848.AIC3254_ADC_I2S_VOL_DAC.zip

This process flows generated the following .cfg file, which works fine in my EVM board:

2110.volume.txt

Then I modified the file to meet requirements of my custom board and removed miniDSP related stuff, playback works fine:

#			--------------------------------------------------------------- page 0 is selected
w 30 00 00
#			# reg[  0][  1] = 0x01	; Initialize the device through software reset
> 01
#			--------------------------------------------------------------- page 1 is selected
w 30 00 01
#			# reg[  1][  1] = 0x08	; Disable weak AVDD to DVDD connection
> 08
#			# reg[  1][  2] = 0x00	; Enable Master Analog Power Control
> 00
#			# reg[  1][ 71] = 0x32	; Set the input power-up time to 3.1ms
w 30 47 32
#			# reg[  1][123] = 0x05	; Force REF charging time to 40ms
w 30 7b 05
#
# miniDSP code goes here
#
#			--------------------------------------------------------------- page 0 is selected
w 30 00 00
#			# reg[  0][ 60] = 0x00	; Use miniDSP_D for signal processing
# w 30 3c 00
#			# reg[  0][ 61] = 0x00	; Use miniDSP_A for signal processing
# > 00
#			# reg[  0][ 17] = 0x08	; 8x Interpolation
w 30 11 08
#			# reg[  0][ 23] = 0x04	; 4x Decimation
w 30 17 04
#			
w 30 0f 03
#			
> 88
#			
w 30 15 03
#			
> 88
#			--------------------------------------------------------------- page 8 is selected
# w 30 00 08
#			# reg[  8][  1] = 0x04	; adaptive mode for ADC
# > 04
#			--------------------------------------------------------------- page 44 is selected
# w 30 00 2c
#			# reg[ 44][  1] = 0x04	; adaptive mode for DAC
# > 04


#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][1 ] = 0x08     ; reg(1)(0x01 => 1 )     Crude avdd disabled
> 08
#     # reg[1][2 ] = 0x01     ; reg(1)(0x02 => 2 )     AVDD LDO power up
> 01
#     # reg[1][10] = 0x03     ;  LDOIN 1,8-3,6V
w 30 0A 03
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][04] = 0x03     ; PLL_clkin = MCLK,codec_clkin = PLL_CLK
w 30 04 03
#     # reg[0][05] = 0xD1     ; PLL Power up, P = 5, R = 1
> D1
#     # reg[0][06] = 0x13     ; J = 19; 80 MHz <= PLL_CLK <= 110 MHz; PLL_CLK = (19.6608/5 * 25MHz) = 98.304MHz
> 13
#     # reg[0][07] = 0x19     ; D = 6608, D(13:8) = 0x19
> 19
#     # reg[0][08] = 0xD0     ; D(7:0) = 0xD0
> D0
#     # reg[0][11] = 0x82     ; NDAC is powered up and set to 2
w 30 0b 82
#     # reg[0][12] = 0x88     ; MDAC is powered up and set to 8
> 88
#     # reg[0][13] = 0x03     ; DOSR = 768, DOSR(9:8) = 0
> 03
#     # reg[0][14] = 0x00     ; DOSR(7:0) = 768
> 00
#     # reg[0][29] = 0x01     ; bdiv_clkin = dac_mod_clk
w 30 1d 01
#     # reg[0][30] = 0x8c     ; blk_N = 12
w 30 1e 8c
#     # reg[0][18] = 0x88      --powerup NADC and value is 8
w 30 12 88
#     # reg[0][19] = 0x8C      --Powerup MADC and value is 12
> 8C
#     # reg[0][20] = 0x40      --AOSR is 128
> 80
#     # reg[0][27] = 0x4c     ; mode is dsp,wordlength is 16, codec is bclk and wclk master
w 30 1b 4c
#     # reg[0][63] = 0xd6     ;11010110b     ; POWERUP DAC left and right channels (soft step disable)
w 30 3f d6
#     # reg[0][81] = 0xc2     ;11000010b     ; -- POWERUP ADC left and left channel (soft step disable)
w 30 51 c2
#     # reg[0][82] = 0x00     ;00000000b     ; -- unmute ADC
> 00



#############################################################
#                       Select Page 1
w 30 00 01
#                      Turn On Mic Bias generated from LDOIN
w 30 33 68
### d 30


###############  IN 3 SET UP START *************************
#
#                      IN2_L is selected for left P 10k
w 30 34 10
#
#                      IN2_R is selected for left M 10k
w 30 36 10
#
#                      IN1_R is selected for right P 10k
w 30 37 40
#
#                      IN1_L is selected for right M 10k
w 30 39 10
#
###############  IN 3 SET UP END ****************************

#                      unmute left mic PGA
w 30 3b 48
#                      unmute right mic PGA
w 30 3c 00
#**********  ENABLE DAC and HP OUTPUTS *********************
w 30 00 01

#########################################################

#                      Power up LOL and LOR driver
w 30 09 0c
#                      LDAC AFIR routed to LOL
w 30 0e 08
#                      RDAC AFIR routed to LOR
w 30 0f 08
#                      LOL unmuted with 0dB gain
w 30 12 00
#                      LOR unmuted with 0dB gain
w 30 13 00
#                      Page 0 selected
w 30 00 00
#                      L&R DAC powerup Ldata-LDAC Rdata-RDAC
w 30 3f d6
#                      DAC left digital PGA
w 30 41 00

#                      Left and Right DAC unmuted with indep.  vol. ctrl
w 30 40 00

Finally I added miniDSP stuff again and when I try a playback I only hear loud noises:

0045.volume_yesdsp.txt

You can easily check differences among "volume_nodsp" and "volume_yesdsp" with kdiff3 or similar programs to see what's changed.

Does this help you out on figuring out the problem?

I still don't have a clue since, apparently, the only thing I'm doing is adding/removing miniDSP stuff.

Thank you.

Ji Javier Martin,

On my EVM I am not seeing the issue. your scripts are working on my EVM with PLL settings changed and Audio Interface settings changed.  So, I think debugging needs to happen on your system.

One your board, playback never worked with miniDSP-enabled, right?

Is it possible to give the ACI3254 related schematics of your board?

Regards,

Mohan Yenigalla said:

One your board, playback never worked with miniDSP-enabled, right?

Yes, with miniDSP enabled playback has never worked. Without miniDSP enabled it does work.

Mohan Yenigalla said:

Is it possible to give the ACI3254 related schematics of your board?

Sure, nothing special there,  here you have the audio related part:

7103.schematic.pdf

Regarding NOPOP components, the current used path is through TPA2012 amplifier.