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Original question:

TLV320AIC3105: New Programmable ADC Digital Path

TLV320AIC3105: Startup sequence (Register setting order)

Koshi Ninomiya
Expert 5685 points
Part Number: TLV320AIC3105


Hi Team,

My customer is reviewing the startup sequence (register setting order) of TVL320AIC3105 now, because they have some issue on their TLV320AIC3105 system. But they did not understand the startup sequence (register setting order) from the TVL320AIC3105 datasheet.

Could you describe the startup sequence (register setting order) of TVL320AIC3105?
* Especially, they want to know the setting procedure of PLL. Because they are worried that if the PLL operates in the middle of setting, it will be unlocked and will not lock after setting.

<Issue>
 - The following situations may occur when the power is turned on. (Frequency is about once every 30 times)
        - Pulse noise is always generated in ms cycle
 - Improve by restarting the power supply or re-executing the IC startup sequence.

<TLV320AIC3105 system>
 - /RESET pin and Registers (through I2C communication) of the TLV320AIC3105 are controlled by ARM processor (ARM Coretex-A9 processor integrated in Xilinx Zynq
 - Clock setting of the TLV320AIC3105 is,
      MCLK: Input
      BCLK: Output
      WCLK: Output
 - Audio digital line is connected with PLL block of Zynq through I2S

Thank you.

Best Regards,

Koshi Ninomiya

  • 0
    TI__Mastermind 22950 points

    Hello Koshi-san,

    The first two writes to the device should be to Register 0 and Register 1. Register 0 sets the Page and Register 1 is to apply a software reset. I recommend these be the first two register that are to be written to. The rest of the registers do not need to be written in a particular order. 

    I should note that there is a power-up sequence that should be followed. Please see the diagram found in Section 12 of the data sheet.

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    TI__Expert 5685 points

    Hi Aaron-san,

    Please continue the support for this thread.

    The customer can duplicate the issue by the following steps, although the incidence of issue is low.
      - The TLV320AIC3105 starts up normally.
      - Change D7 BIt setting of "PLL Programming Register A" from "D7=1: PLL is enabled" to "D7=0: PLL is disabled" to "D7=1: PLL is enabled"
      - The issue (Pulse noise is always generated in ms cycle) occurs with a low probability.

    Are there any relation between the issue and PLL register setting?

    Are there any relation between the issue and the sequence from RESET=High to writer order to registers?

    Thank you.

    Best Regards,

    Koshi Ninomiya

  • 0 in reply to Koshi Ninomiya
    TI__Mastermind 22950 points

    Hello Koshi-san,

    Are you saying the customer will disable the PLL then enable it? By default the PLL is enabled. Why would they disable it only to re-enable it?

    It could also be the way the PLL is configured. Can you send over the MCLK frequency they are using along with their register settings. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    TI__Expert 5685 points

    Hi Aaron-san,

    The customer did set PLL enable --> disable --> enable, because they tried to analyze root cause of this issue, tried to duplicate this issue for root cause analysis.

    Please let me check about your suggestion. 
    The TLV320AIC3105 supports the I2C standard mode and fast mode for register setting.
    In case of I2C fast mode, SCL supports up to 400kHz.
    On the other hand, MCLK frequency is from 512kHz to 50MHz, it is higher than SCL fast mode frequency.
    Could you explain more about "send over the MCLK frequency they are using along with their register settings"?
    Thank you.

    Best Regards,

    Koshi Ninomiya

  • 0 in reply to Koshi Ninomiya
    TI__Expert 5685 points

    Hi Aaron-san,

    I look forward to your reply for the following,
    ***********************************************************************************************************************************
    Please let me check about your suggestion. 
    The TLV320AIC3105 supports the I2C standard mode and fast mode for register setting.
    In case of I2C fast mode, SCL supports up to 400kHz.
    On the other hand, MCLK frequency is from 512kHz to 50MHz, it is higher than SCL fast mode frequency.
    Could you explain more about "send over the MCLK frequency they are using along with their register settings"?
    ***********************************************************************************************************************************

    Additional information, the customer's frequency settings are as follows,
    　SCL(I2C) : 400kHz
    　MCLK : 48MHz
    　PLL_P : 4
    　PLL_R : 1
    　PLL_J : 8
    　PLL_D : 1920
              * PLL settings are the same as the bottom of the table on page 25 of "10.3.3.1 Audio Clock Generation"

    Please let me know if there are any doubts that lead to their issue.
    Thank you.

    Best Regards,

    Koshi Ninomiya

  • 0 in reply to Koshi Ninomiya
    TI__Mastermind 22950 points

    Hello Koshi-san,

    Is the PLL being enabled and disabled while the device is running? If so, I do not recommend this as they were not designed to change while the device is running. Changing the PLL should only be necessary if going from a multiple of 44.1k to a multiple of 48k, or when changing the PLL_IN clock. 

    Regards,

    Aaron

  • 0 in reply to Koshi Ninomiya
    TI__Mastermind 30220 points

    Koshi, 

    Just wanted to provide a quick add on to what Arron has mentioned. 

    1.  The PLL Coefficients should all be programed first,  Then the PLL enabled in a separate transaction.  (you should not be changing coefficients while the PLL is enabled)

    2. The ADCs/DACs should not be powered up when the PLL is enabled or disabled.  This should not come as a surprise

    best regards,

    -Steve Wilson