Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 328 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM1774: Clocking question

Marion Loessl
Expert 3470 points
Part Number: PCM1774

Hi!

my customer uses PCM1774 and has the following questions:

------------------------------------------------------------------

PCM1774 is used associated with a Silicon Lab CP2114.

 

The CP2114 generates 3 clocks to the PCM1774.

-          One clock MCLK at 12MHz connected to the input SCKI of the PCM1774

-          One clock SCK at 48MHz/14=3.428MHz connected to the input BCK of the PCM1774

-          One clock LRCK at 12MHz/250=48kHz connected to the input LRCK of the PCM1774

 

What is the good setting for the register @ 0x55 ? (NPR[5:0] register).

 

We set this register to 0x04h (00 0100).

Is it the good setting for this register ?

 

In the PCM1774 what is called the sampling rate ?

--------------------------------------------------------------

Kind regards,

Marion

  • 0
    TI__Guru 53433 points

    Hi Marion,

    An SCK divider of 250 is not supported by the PCM1774.  I have seen this problem with the CP2114 before.  They will need to use the external MCLK option for the CP2114 to provide the ~49MHz clock to generate a SCLK of fs×256 or an external 48MHz clock to generate the 12MHz USB clock.

    There I recall that a few posts have been made on the SiLabs forum about this as well.  

    thanks,

    Paul