We've been using this part for some months, and have continued to get this overflow bit set. Audible artifacts are being heard. We are at our wits end on this issue. I've searched this forum and come up with almost nothing. We've disabled the biquad filters that we normally have active, so the DAC chain using PRB_P2 should be clean & unable(?) to generate this overflow. We've eliminated volume as a possibility, setting it to 1. So, specifically, what conditions can cause the overflow bit to get set? Some notes:
1) Although enabled for interrupts, unfortunately the line is not physically tied to our MCU; wire for scope probe only. MCU detection is via reading register 42.
2) Clocking is via the I2S clock; 0's are fed on the data line. DMA is being used to feed the data.
3) At one point, we did have 'bad data' being fed in on the I2S, in the sense that large data shifts were taking place. That was fixed(?).
thanks
static constexpr PRVTriplet AudioFirstStageInit[] =
{
// rsv [00], LDO 1.8v [00], PLL level shifters on [0], rsv [000]
// from TI, though data sheet says to write D2=1 (rsv [100])
{0x01, 0x02, 0x00},
{0x00, 0x04, 0x07}, // rsv [000000], BCLK -> PLL, PLL -> CODEC_CLKIN
{0x00, 0x05, 0x92}, // PLL enabled, PLL_P=1, R=2
{0x00, 0x06, 0x3C}, // PLL_J=60
{0x00, 0x07, 0x00}, // seqential write to 0x07/0x08, PLL_D=0
{0x00, 0x08, 0x00} // part of a register pair write
};
static constexpr PRVTriplet AudioSecondStageInit[] =
{
// Page / Register / Data
{0x00, 0x0B, 0x83}, // NDAC powered up [1], NDAC=3 [0000011]
{0x00, 0x0C, 0x8A}, // MDAC powered up [1], MDAC=10 MDAC [0001010]
{0x00, 0x0D, 0x00}, // sequential write to DOSRmsb:DOSRlsb, DOSR = 128
{0x00, 0x0E, 0x80}, // Part of a register pair write
{0x00, 0x1B, 0x00}, // I2S[00], 16 bits [00], BCLK in [0], WCLK in [0], rsv[00]
{0x00, 0x1C, 0x00}, // data offset 0
{0x00, 0x3C, 0x02}, // rsv[000], PRB_P2 processing block [00010]
// BQ A Filters ------------------------------------
// The following values represent a 200 Hz High-Pass Filter
// N0 0x7AF18F
#if BQA==1
{0x2C, 0x0C, 0x7A}, // N0 Coefficient for DAC filter reg 12
{0x2C, 0x0D, 0xF1}, // N0 Coefficient for DAC filter reg 13
{0x2C, 0x0E, 0x8F}, // N0 Coefficient for DAC filter reg 14
// N1 0x850E71
{0x2C, 0x10, 0x85}, // N1 Coefficient for DAC filter reg 16
{0x2C, 0x11, 0x0E}, // N1 Coefficient for DAC filter reg 17
{0x2C, 0x12, 0x71}, // N1 Coefficient for DAC filter reg 18
// N2 0x7AF18F
{0x2C, 0x14, 0x7A}, // N2 Coefficient for DAC filter reg 20
{0x2C, 0x15, 0xF1}, // N2 Coefficient for DAC filter reg 21
{0x2C, 0x16, 0x8F}, // N2 Coefficient for DAC filter reg 22
// D1 0x7AD7FE
{0x2C, 0x18, 0x7A}, // D1 Coefficient for DAC filter reg 24
{0x2C, 0x19, 0xD7}, // D1 Coefficient for DAC filter reg 25
{0x2C, 0x1A, 0xFE}, // D1 Coefficient for DAC filter reg 26
// D2 0x89E9BC
{0x2C, 0x1C, 0x89}, // D2 Coefficient for DAC filter reg 28
{0x2C, 0x1D, 0xE9}, // D2 Coefficient for DAC filter reg 29
{0x2C, 0x1E, 0xBC}, // D2 Coefficient for DAC filter reg 30
#endif
#if BQB==1
// BQ B filters ------------------------------------
// The following values represent a 4000 Hz Low-Pass Filter
// N0 0x2AD98F
{0x2C, 0x20, 0x2A}, // N0 Coefficient for DAC filter reg 32
{0x2C, 0x21, 0xD9}, // N0 Coefficient for DAC filter reg 33
{0x2C, 0x22, 0x8F}, // N0 Coefficient for DAC filter reg 34
// N1 0x2AD98F
{0x2C, 0x24, 0x2A}, // N1 Coefficient for DAC filter reg 36
{0x2C, 0x25, 0xD9}, // N1 Coefficient for DAC filter reg 37
{0x2C, 0x26, 0x8F}, // N1 Coefficient for DAC filter reg 38
// N2 0x2AD98F
{0x2C, 0x28, 0x2A}, // N2 Coefficient for DAC filter reg 40
{0x2C, 0x29, 0xD9}, // N2 Coefficient for DAC filter reg 41
{0x2C, 0x2A, 0x8F}, // N2 Coefficient for DAC filter reg 42
// D1 0xF593A1
{0x2C, 0x2C, 0xF5}, // D1 Coefficient for DAC filter reg 44
{0x2C, 0x2D, 0x93}, // D1 Coefficient for DAC filter reg 45
{0x2C, 0x2E, 0xA1}, // D1 Coefficient for DAC filter reg 46
// D2 0xE97281
{0x2C, 0x30, 0xE9}, // D2 Coefficient for DAC filter reg 48
{0x2C, 0x31, 0x72}, // D2 Coefficient for DAC filter reg 49
{0x2C, 0x32, 0x81}, // D2 Coefficient for DAC filter reg 50
// End of filter values
{0x01, 0x01, 0x10}, // rsv [000], master ref on [1], POR on [0], rsv [0], LDO up [0], rsv [0]
{0x01, 0x0A, 0x00}, // rsv [0], common mode 0.9v [0], rsv [0], HP full drive [0], rsv [00]
// no analog routing [0000], DAC routed to Mixer M [0],
// Mixer P not routed to HP atten [0], AINL/R atten routing off [00]
{0x01, 0x0C, 0x00},
{0x01, 0x16, 0x75}, // rsv [0], HP muted [111 0101]
{0x01, 0x18, 0x75}, // Mixer M & P disabled [0], AINL muted [111 0101]
{0x01, 0x19, 0x75}, // rsv[0], AINR muted [111 0101]
{0x01, 0x09, 0x00}, // rsv [00], HP powered down [0], rsv [00], AINL/R disabled [00]
{0x01, 0x10, 0x40}, // rsv [0], HP muted [1], HP gain 0 dB [000000]
{0x01, 0x2E, 0x00}, // rsv [0], SPK atten 0 dB [000 0000]
{0x01, 0x30, 0x10}, // rsv [0], unmute output driver, gain +6 dB [001], rsv [0000]
{0x01, 0x2D, 0x02}, // rsv[0000 00], SPK power up [1], rsv[0]
// DAC powered up [1], rsv [0], left ch->DAC [01],
// rsv [00] (from TI, instead of 01), soft step 1 per WCLK [00]
{0x00, 0x3F, 0x90},
{0x00, 0x41, 0x00}, // DAC digital volume = 0dB [00000000]
// rsv [0], auto-mute off [000], unmute DAC [0], rsv [000] (from TI, instead of [100]
{0x00, 0x40, 0x00},
// DAC overflow interrupt
{0x00, 0x30, 0x05}, // INT1 DAC overflow; pulse train
{0x00, 0x34, 0x14} // GPIO as INT1 output
#endif
