Hello,
Our customer wants to get TI's suggestion about PLL start condition.
On the datasheet described as below, SCK should be GND level for 16 LRCK periods.
However they have verified what happen if SCK keep H level for 16 LRCK periods. Then PLL is started normaly.
Can they expect PCAM5101A's PLL can start at SCK input is both of GND or H level hold condtion?
9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source
reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency
electromagnetic interference.
The internal PLL is disabled as soon as an external SCK is supplied.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock. Table 11
describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an
internal SCK.
Regards,
Mochizuki
