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TLV320AIC3104-Q1: The MCLK of TLV320AIC3104 in master mode

Always-On-Line
Prodigy 80 points
Part Number: TLV320AIC3104-Q1
Other Parts Discussed in Thread: TLV320AIC3104

Hi expert：


About the codec TLV320AIC3104 ,in our case,it is in the master mode,now we want to know that:

How to generate the MCLK to TLV320AIC3104,and what type clock it can received,an external  OSC?but it output the sinewave,psl help to confirm.

Thanks!

  • 0
    TI__Mastermind 22950 points

    Hello,

    The MCLK is commonly produced by the host processor and is used to generate ADC and DAC Fs. The CODEC_CLK must always = 256*Fsref. Fsref can only be 48k or 44.1k. So on the AIC310x devices this must be 12.288Mhz or 11.2896Mhz (48/44.1).The CODEC can also use the BCLK for CODEC_CLK and MCLK may be left unconnected. 

    I am not sure what you mean by "but it output the sinewave" . What outputs a sine wave? Can you elaborate?

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 80 points

    Thanks for your reply.

    In our case, the Codec is in master mode,the Processor is in the slave mode,and do not have the MCLK),so how to get the the MCLK?In my view,it can be generate by a external Crystal Oscillator,in this condition,the MCLK of codec will reveive a analog clock input(sinewave).

    Best Wishes！

  • 0 in reply to Always-On-Line
    TI__Mastermind 22950 points

    Hello,

    Thanks for your reply! The MCLK input should be a square wave. Like I mentioned above, BCLK can be used instead of MCLK for ADC and DAC Fs. Check registers 105 and 106.

    Regards,
    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 80 points

    Hi：

    If the codec is in master mode,it means that the BCLK is a output,just like the plot:

    In this case, we need another clock source,if use the external OSC,it should be a sinewave input.

  • 0 in reply to Always-On-Line
    TI__Mastermind 22950 points

    Hello, 

    Yes this is true but with the AIC310x family, with the PLL enabled, you can select the BCLK to be used to generate ADC/DAC Fs. This will eliminate having to use MCLK. 

    Unless your processor needs an MCLK, then in this case, yes, use an oscillator to generate square-wave (not sine-wave). When using an oscillator, we suggest using the PLL to help with any CLK jitter. For more information, please see section 10.3.3.1 in the data sheet for more information.

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 80 points

    Hi：

    I'm  confused about your audio clock generation solution,I know that  the BCLK can be used to generate ADC/DAC Fs,but how we can get the BCLK? In my view, this just limitted to as the slave for codec.

    Now,in our case,the codec is in the master mode,and the bclk is output to processor,with the PLL enabled,the PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5 to D4,then

    we also need a clock source(how to get the BCLK?).

    If we have to use a oscillator,the PLL  enable just contribute to generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

    can you help offer a optional and appropriate oscillator component for us that can generate a square-wave?

    Thanks!

  • 0 in reply to Always-On-Line
    TI__Mastermind 22950 points

    Hello,

    My apologies. I was a bit confused earlier. 

    Using TI's parametric search, I came across LMK62I0-100M. This is a reference clock generator with low jitter and a max frequency of 100MHz. This should do the trick. 

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 80 points

    ok,I will check it and thank you very much for your support!