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TLV320ADC6140: Configuring as Audio Serial Interface Master

Sean Heffernan1
Intellectual 290 points
Part Number: TLV320ADC6140

I wish to use the TLV320ADC6140 to sample two differential input signals, and I would like to configure the ADC to operate as the Master of the Audio Serial Interface. It is my understanding that I need to provide an external MCLK source to the device, is this correct? If so, can I connect MCLK to any of the unused GPIx inputs, or is there a specific pin that must be used?

  • 0
    TI__Guru 63965 points

    Hello,

    Yes, you'll need to feed in an MCLK signal to operate the device in master mode.  We have a soon-to-release app note with more information on the configuration which I've attached the final, but unpublished version of here.  We recommend connecting the MCLK to GPIO1 in the app note.

    **App note should be released in next couple of days and file will be replaced with a link:

    Configuring and Operating TLV320ADCx140 as Audio Bus Master

    2.1.1.2 Example 12MHz MCLK

    For a 12MHz MCLK, the following I2C script configures the TLV320ADCx140 as master mode with GPIO1
    as MCLK input for 44.1kHz or 48kHz sampling rate:
    w 30 21 a0 # configure GPIO1 as MCLK input
    w 30 13 80 # configure device as Master with MCLK = 12 MHz
    w 30 14 48 # FS = 44.1/48k BCLK/ratio = 256

  • 0 in reply to Collin Wells
    Intellectual 290 points

    Thanks Collin.

    We are planning to sample 2 channels. From the datasheet, it looks like the ADC can be configured to output a second data stream (SDOUT2). Does this mean that we could use a single set of FSYNC/BCLK signals to output the data from both channels simultaneously in parallel (on SDOUT and SDOUT2)?

    If so, the datasheet says that GPIO1 must be used for SDOUT2 to achieve high-speed AIS output rates. So I'm going to design my board to feed MCLK into GPI4, and use GPIO1 for SDOUT2. Does this sound reasonable?

    Sean

  • 0 in reply to Sean Heffernan1
    TI__Guru 63965 points

    Hi Sean,

    That would work, but keep in mind that I2S, LJ, RJ, and TDM options already support two channels (or more) on a single SDOUT line so the 2nd SDOUT may not be required in your application.

  • 0 in reply to Collin Wells
    Intellectual 290 points

    Collin,

    I understand that those options support 2 channels on a single SDOUT, and that was our original intention. But we would like to sample as fast as possible, and it seems as if throughput on SDOUT is our limiting factor. If we can output data on two SDOUT lines simultaneously, we can double the throughput, which means that we SHOULD be able to sample twice as fast. Does that sound right?

  • 0 in reply to Sean Heffernan1
    TI__Expert 6995 points

    Sean,

    Yes, you can send data on two SDOUT lines simultaneously, as long as they are different channels. You will need to configure:

    • ASI_CH1 register to sent output on the ASU primary output in
    • ASI_CH2 register to sent output on secondary pin and assign the slot-0
    • GPIO_CFG0 to map GPIO1 as secondary ASI output

    best regards,

      Pedro