Hi,
Is my understanding correct that PCM1753 perform the dc offset calibration for the outputs of VOUTL and VOUTR during the reset period(1024 system clocks)?
It seems that the dc offset is cancelled when observing VOUTL and VOUTR.
Best regards,
Kato
You have a few threads open about this topic, so the answers will probably be similar in each one.
The PCM175x is an older device and it does not have much clock error protection circuitry. There is a risk of a pop noise whenever the delta-sigma modulator starts or stops, or when there is a clock error. Basically, when the DSM is switching, there is no sudden DC change (besides those desired from the digital input source), but if there is a clock error, the DSM stops. During a stop, the ~7 current segments go to a DC state, that can be different than the VCOM voltage. This abrupt stop can sound like a pop or glitch if the magnitude is large enough.
At startup, the device will enable the DSM modulator, but it has no clock to use as a switching source. This means that some of the current segments will be on and others will be off. Usually, the number that is off and on are the same so the output is approximately the VCOM value. That is not guaranteed to the be case.
The image above shows the behavior of the device when I2S is applied for the first time and then stopped. The blue line is VCM, the yellow and green are VOUTL and VOUTR, and the orange line is one of the I2S signals. You can see that the DSM starts and stops from a static DC offset. These can be audible in some systems.
The only way to avoid this is to implement an external mute functionality that can be asserted when there is a clock error, but that error detection would need to come from the I2S source rather than the PCM175x.
Thanks,
Paul
