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Original question:

TLV320ADC6140: Audio Signal Input Channel Selection at 384kHz sampling rate

TLV320ADC6140: Audio Serial Interface / I2S Mode Standard Protocol Timing

Koshi Ninomiya
Expert 5435 points
Part Number: TLV320ADC6140

Hi Team,

My customer is considering to use the TLV320ADC6140 as audio ADC with 384kHz sampling rate and I2S Audio Serial Interface.

My customer understand that the communication frame consists of 64 slots (Right 32 slots, Left 32 slots in I2S), and they recognize that it can be assigned to any slot (output order) and output by specifying slot in the channel register.

However, referring to the Figure 27. I2S Mode Standard Protocol Timing (TX_OFFSET = 0) of 8.3.1.2.2 Inter IC Sound (I2S) Interface, it seems that repeated communication is made in a total of 8 slots of Left Slot-0 ~ Slot-3 ad Right Slot-0 ~ Slot-3.

Q1: In actual operation, which one is correct, 64 slots output repeatedly, or only the slot with the setting flowed in the slot number order (maximum 8 slots)?

Q2: If 2 channels analog differential input are set as below, please tell them whether Left Slot-1 is output with empty data, or the data after Slot-0 becomes Slot-2 data immediately and other slots are not output. .Or if their understand is not correct, please tell them the detailed specifications.
CH1_SLOT [5: 0] = 0d  --> Left Slot-0
CH3_SLOT [5: 0] = 02  --> Left Slot-2

Q3: Left / Right is a classification based on the I2S communication standard. When using analog differential input, does it not matter if they specify each slot to any slot?
Example) All Left, etc.

Best Regards,

Koshi Ninomiya

  • 0
    TI__Expert 6995 points

    Koshi-san,

    The TLV320ADx140 devices support three types of Audio Serial Interface (ASI) through the ASI_FORMAT (Page 0, ASI_CFG0 Register 0x07, Bits 7-6) = 2’b10 (LJF format):

    • TDM (up to 64 slots),
    • I2S-like with up to 32 left and up to 32 right slots, and
    • Left-Justified Mode (LJ or LJF)with up to 32 left and up to 32 right slot.

    The user program's which channels are output into a specific slot through the CHx_OUTPUT (Page 0, ASI_CHx Register 0x0B-0x12) and also which slot is enabled in the ASI bus. Furthermore, the following settings are configurable:

    • BCLK_POL (Page 0, ASI_CFG0 Register 0x07, Bit 2)
    • TX_EDGE (Page 0, ASI_CFG0 Register 0x07, Bit 1)
    • FSYNC_POL (Page 0, ASI_CFG0 Register 0x07, Bit 3)

    The app note Configuring and Operating TLV320ADCx140 as Audio Bus Master show the effect of these registers configurations.

    Only the slots for enabled channels that are configured on ASI_Chx are outputted. So for example, if CH1 and CH3 are enabled, but CH2 is not enabled and they are configured as:

    • CH1_SLOT [5: 0] = 0d --> Left Slot-0
    • CH3_SLOT [5: 0] = 02 --> Left Slot-2

    The ASI bus will have Ch1 on Slot 0, Slot 2 unoccupied, and then Ch3 in Slot 3. The state of SDOUT in between Slot 0 and Slot 2 depends on the setting of TX_FILL (page 0, ASI_CFG0 Register 0x07, bit 0) to be either Hi-Z for unused slots or driven low.

    The assignment of a channel to a slot is arbitrary. I2S assumes some to be right or left channel. The CHx_OUTPUT (Page 0, ASI_CHx Register 0x0B-0x12) allows the user full flexibility in making these assignments. This is useful if the board routing needs to be swapped or to have one board for multiple applications where the channel selection is performed through software instead of having different versions of boards for different applications.

    Best regards,
    Pedro