hi，any one who concerns~
I have a question using tlv320aic3104.
We connect this codec chip to FPGA and want to test the loopback path where DIN goes into the serial interface and goes back to DOUT through the path show below. Is that accessible by the following steps described in datasheet page40? THX.
1. power down all DACs and ADCs；
2. enable digital filter pathway for ADC by writing 1 to page 0,register 107,bit3.
hi, Aaron
This is also Nessee. There seems some trouble with my preview account, so I register a new one.
Back to the question I raised above, we had done some experiment on the loop back test, however it did not work properly. We configured the register , and we put some test data on DIN pin，we got nothing out from DOUT pin .
(1)The registers we configed and read are below ：
register 37=0，
register 19,22=0x78，
register 107=0x8
(2)We did another test. When turning ON the ADC & PGA while remaining the same configuration above , the data we got in mem is pretty much like what we got when doing recording experiment.
So ，I wonder if this chip TLV320AIC3104 can really realize the function of loop back ,which means when I turn OFF both ADC & DAC , and the data flows from DIN to DOUT. Is there anything we missed when configuring? Looking forward to your reply. THX~
