Gregg/Robert:
Thanks for the design assistance both of you have given me in recent days.
Although this is an inside observation that might be meaningless to you, I've been able to run my prototype board at 150 amps load current with a variety of complex ANSI waveforms. No capacitors whatever in the reconstruction filter, just a 470uH toroid on each channel output.
I'm probably your only customer running this part as a low phase shift, 20 watts per channel quad op amp. The boss is pleased and I'm ready to go a pre-production lay-out.
The most current data sheet I have is labeled SLASEP6A REVISED NOVEMBER 2019. Anything more current to share?
If not, could these questions be answered tentatively:
1. Output DC Offset Voltage. If I manage the device's input DC offset voltage to be in the microvolt area relative to IN_M using high-quality TI op amps, approximately how much output DC offset voltage might I see? Over reasonable die temps? The matter concerns me because my output current transformers are allergic to DC.
2. Setting I2C Address. My early data sheet mentions that current into the /FAULT pin during an early blip low configures the I2C address. What are the resistance bands and center points for the two addresses? Do these resistance values track with the DVDD voltage and (due to the narrowness of the bands) disallow pulling the pin up to a high precision +3.3VDC rail elsewhere?
Exactly when does the /FAULT pin blip low to set the I2C address? Can I exert any control over this read time without gating the IC's power supply with a relay?
The basis for this timing question: unlike most users I will not have a single pull-up resistor to DVDD on the /FAULT pin. Instead I will have one of two resistors to DVDD chosen by another system PCB that does not share TPA6304's power supply. Thus I might be forced to resolve a timing contest over which PCB powers up first.
Thanks. Great part! TI rocks.
