[FAQ] TLV320ADC5140: MCLK Input Clock Requirements

1.) The maximum input frequency is:  36.864MHz.

2.)  Duty-Cycle min/max is 45% and 55% respectively

3.)  Jitter should be <1ns if the PLL will be used with the MCLK as an input

4.)  Logic level glitches or other noise on the clock input must be avoided.  Glitches may trigger a clock error which will shut down the ASI.  Please keep the MCLK input signal as clean as possible by adding some series resistance (10-33 Ohms) near the output drivers, avoiding long adjacent trace routing with other switching signals, and possibly adding some shunt capacitance if the glitches are sourced extrinsically.