• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 481 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM1808: Conversion delay

Amy Luo
Expert 6895 points
Part Number: PCM1808
Other Parts Discussed in Thread: PCM1840

Hi team,

What is the delay time of PCM1808 from analog signal input to I2S signal output, or how to calculate it?

According to the description of ‘7.4.2 clock halt power down and reset function’ on page 18 of the datasheet, the delay should be 1024 SCKI + 8960 / fs, and 48 / fin or 48 / fs extra time is required to perform the fade-in operation. Is that so?

The customer wants to choose an audio ADC with a small delay time. The requirements are as follows. Is there a better recommendation?

1. Two line in inputs

2. Ready to use 48Khz sampling rate

Best Regards,
Amy Luo

  • 0
    TI__Mastermind 23050 points

    Hi Amy, 

    The conditions you have described are more concerning the delay from startup. Is your customer concerned about the startup time coming out of reset or just the latency of the signal under steady-state operating conditions? If it is the latency, then this is largely set by the decimation filter and is specified as 17.4/fs. Since your customer want to use 48kHz sample rate, the latency would be around 362us. If this is too much, you could consider using the PCM1840, which is a much higher performance hardware controlled ADC released recently. This device has the option to select a low latency filter with a delay of 7.7/fs at 48kHz, or 160us.

    Best,

    Zak