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PCM1862: Can scenario work

M.A.M
Expert 8925 points
Part Number: PCM1862


Hi,

My customer wonder if the PCM1862 can support 24.576MHz bit clock as slave, and tolerate a longer frame sync interval than usual?

Here is the scenario:

Fs = 48KHz
Wl = 24bit
Mclk/Sclk = 24.576MHz from Master
Bclk = 24.576MHz from Master
Wclk = TDM16 Frame = 512 x BCLK (TDM16 = 16X32bit)

It is OK if the first two TDM slots are used for data transmission, but it should wait nicely in Hi-Z until start of next frame, 512 bitclocks later.

Thanks.

B.r M.A.M

  • 0
    TI__Mastermind 23050 points

    Hi,

    PCM1862 will keep its data output Hi-Z when not transmitting as long as it is still being clocked. It supports either 50% duty cycle WCLK/LRCK or 1 bit clock pulse. The only limitation is that the PCM1862 can only offset its data output by up to 256 BCK cycles, but if you are using the first two TDM slots then this is not an issue.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 8925 points

    Thanks Zak.

    Last question: Max BCK in slave mode can be interpreted as 3MHz. Period min is said to be  1/(64 x fs).

    Is 24.576MHz BCK possible to receive  from a master in slave mode?

    B.r M.A.M

  • 0 in reply to M.A.M
    TI__Mastermind 23050 points

    Hi, 

    The BCK limitation mentioned in table 7.11 is actually inaccurate in the datasheet right now. I have tested this to confirm the device operates just fine with higher BCKs and have this on a list of things to update. The maximum supported BCK is 25MHz with 1.8V IOVDD and 50MHz with 3.3V IOVDD as shown in table 7.8

    Best,

    Zak