Square Wave is getting severely distorted while passing through the codec as shown in the screenshots below. The distortion happens after the ADC:
Square Wave – 10 Hz
Square Wave – 200 Hz
Square Wave – 1 kHz
My codec initialization is as such:
AIC3106_write_reg(0, 0x00); // AIC3106_PAGESELECT is PAGE 0 REG 0 AIC3106_write_reg(1, 0x80); // reset AIC3106 using REG 1 // set up sampling rate - default 8kHz AIC3106_write_reg(2, 0xAA); AIC3106_write_reg(7, 0x0A); // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT] AIC3106_write_reg(3, 0x22); // disable PLL and set Q=4(relevant) and P=2(irrelevant) // fsref will be MCLK/(128*Q) = 48000 // MCLK on eXperimenter is 24.576MHz from on-board Citizen oscillator AIC3106_write_reg(4, 0x20); // J=8 (irrelevant since PLL disabled) AIC3106_write_reg(5, 0x6E); // D=7075 MS bits (irrelevant since PLL disabled) AIC3106_write_reg(6, 0x23); // D=7075 LS bits (irrelevant since PLL disabled) AIC3106_write_reg(8, 0xC0); // Audio Interface Control A BCLK=Slave(input), WCLK=Slave(input) AIC3106_write_reg(9, 0x40); // Audio Interface Control B DSP mode (1 slot), 32 bit slot width AIC3106_write_reg(12, 0x00); // Audio Interface Control C Data offset=0 AIC3106_write_reg(10, 0x00); // Audio Interface Control C Data offset=0 // WARNING - this assumes that adc_gain is a sensible value AIC3106_write_reg(15, adc_gain); // Left ADC Programmable Gain Amplifier Mute=OFF Gain=0dB AIC3106_write_reg(16, adc_gain); // Right ADC Programmable Gain Amplifier Mute=OFF Gain=0dB AIC3106_write_reg(19, 0x04); // power up ADCs AIC3106_write_reg(22, 0x04); AIC3106_write_reg(37, 0xE0); // DAC Power & Output Dvr LeftDAC=ON, RightDAC=ON, HPLCOM=SingleEnd] // WARNING - this assumes that dac_atten is a sensible value AIC3106_write_reg(43, dac_atten); // Left DAC Digital Volume Mute=OFF, Gain=0dB AIC3106_write_reg(44, dac_atten); // Right DAC Digital Volume Mute=OFF, Gain=0dB AIC3106_write_reg(82, 0x80); // was 0x80 DAC_L1 to LEFT_LOP/M Volume Routed, Gain=0dB AIC3106_write_reg(86, 0x09); // LEFT_LOP/M Output Mute=OFF bit3 bit0 is REad only ?! must be set! AIC3106_write_reg(92, 0x80); // was 0x80 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed] AIC3106_write_reg(93, 0x09); // 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON] AIC3106_write_reg(101, 0x01); // 101 GPIO Control Register B <- [CODEC_CLKIN = CLKDIV_OUT] AIC3106_write_reg(102, 0);
I was wondering if there is a setting in the codec that could fix this problem.
Thank you!
