Part Number: LM49352
We want to use this codec in 16 & 24 bit data width mode using I2S interfacing
The device will be I2S slave for both Tx and Rx directions.
Our I2S master always generates 32 bit clocks per sample (64 for stereo) even if using only 24 or 16 bits data width. Would the device know how to handle this or does it always need an equal number of bit clocks compared to the data width.
 
				 
		 
					 
                           
				