Part Number: TLV320AIC3254
Hello,
Our customer used TLV320AIC3254 and met a question, please refer to the LINEOUT output, and we found that the amplitude is smaller than the original audio, the step frequency is 100HZ, total frequency range is 100Hz~3000Hz, so the abnormal frequency range is 100Hz-1000Hz.
Could you please help to analysis?
Note: The above one is the output of LINEOUT, and the below wave is the original audio.
Best regards
Kailyn
Hi Collin,
Thank you for your reply.
Below is the output circuit. And I have attached the configuration, one is the configuration before play, and the other is the configuration during play. Please help to confirm.
aic32x4 read: reg 0: 0x0 aic32x4 read: reg 1: 0x0 aic32x4 read: reg 2: 0x60 aic32x4 read: reg 3: 0x0 aic32x4 read: reg 4: 0x3 aic32x4 read: reg 5: 0x11 aic32x4 read: reg 6: 0x7 aic32x4 read: reg 7: 0x14 aic32x4 read: reg 8: 0x90 aic32x4 read: reg 9: 0x0 aic32x4 read: reg 10: 0x0 aic32x4 read: reg 11: 0x2 aic32x4 read: reg 12: 0x8 aic32x4 read: reg 13: 0x0 aic32x4 read: reg 14: 0x80 aic32x4 read: reg 15: 0x2 aic32x4 read: reg 16: 0x0 aic32x4 read: reg 17: 0x8 aic32x4 read: reg 18: 0x2 aic32x4 read: reg 19: 0x8 aic32x4 read: reg 20: 0x80 aic32x4 read: reg 21: 0x1 aic32x4 read: reg 22: 0x0 aic32x4 read: reg 23: 0x4 aic32x4 read: reg 24: 0x0 aic32x4 read: reg 25: 0x0 aic32x4 read: reg 26: 0x1 aic32x4 read: reg 27: 0x0 aic32x4 read: reg 28: 0x0 aic32x4 read: reg 29: 0x1 aic32x4 read: reg 30: 0x4 aic32x4 read: reg 31: 0x0 aic32x4 read: reg 32: 0x0 aic32x4 read: reg 33: 0x0 aic32x4 read: reg 34: 0x0 aic32x4 read: reg 35: 0x0 aic32x4 read: reg 36: 0xcc aic32x4 read: reg 37: 0xaa aic32x4 read: reg 38: 0x0 aic32x4 read: reg 39: 0x0 aic32x4 read: reg 40: 0x0 aic32x4 read: reg 41: 0x0 aic32x4 read: reg 42: 0xe aic32x4 read: reg 43: 0x0 aic32x4 read: reg 44: 0x0 aic32x4 read: reg 45: 0x0 aic32x4 read: reg 46: 0x0 aic32x4 read: reg 47: 0x0 aic32x4 read: reg 48: 0x0 aic32x4 read: reg 49: 0x0 aic32x4 read: reg 50: 0x0 aic32x4 read: reg 51: 0x0 aic32x4 read: reg 52: 0x0 aic32x4 read: reg 53: 0x12 aic32x4 read: reg 54: 0x2 aic32x4 read: reg 55: 0x2 aic32x4 read: reg 56: 0x2 aic32x4 read: reg 57: 0x0 aic32x4 read: reg 58: 0x0 aic32x4 read: reg 59: 0x0 aic32x4 read: reg 60: 0x1 aic32x4 read: reg 61: 0x1 aic32x4 read: reg 62: 0x0 aic32x4 read: reg 63: 0x14 aic32x4 read: reg 64: 0xc aic32x4 read: reg 65: 0xf7 aic32x4 read: reg 66: 0xf7 aic32x4 read: reg 67: 0x0 aic32x4 read: reg 68: 0x6f aic32x4 read: reg 69: 0x38 aic32x4 read: reg 70: 0x0 aic32x4 read: reg 71: 0x0 aic32x4 read: reg 72: 0x0 aic32x4 read: reg 73: 0x0 aic32x4 read: reg 74: 0x0 aic32x4 read: reg 75: 0xee aic32x4 read: reg 76: 0x10 aic32x4 read: reg 77: 0xd8 aic32x4 read: reg 78: 0x7e aic32x4 read: reg 79: 0xe3 aic32x4 read: reg 80: 0x0 aic32x4 read: reg 81: 0xc0 aic32x4 read: reg 82: 0x44 aic32x4 read: reg 83: 0x13 aic32x4 read: reg 84: 0x13 aic32x4 read: reg 85: 0x0 aic32x4 read: reg 86: 0x0 aic32x4 read: reg 87: 0x0 aic32x4 read: reg 88: 0x7f aic32x4 read: reg 89: 0x0 aic32x4 read: reg 90: 0x0 aic32x4 read: reg 91: 0x0 aic32x4 read: reg 92: 0x0 aic32x4 read: reg 93: 0x0 aic32x4 read: reg 94: 0x0 aic32x4 read: reg 95: 0x0 aic32x4 read: reg 96: 0x7f aic32x4 read: reg 97: 0x0 aic32x4 read: reg 98: 0x0 aic32x4 read: reg 99: 0x0 aic32x4 read: reg 100: 0x0 aic32x4 read: reg 101: 0x0 aic32x4 read: reg 102: 0x0 aic32x4 read: reg 103: 0x0 aic32x4 read: reg 104: 0x0 aic32x4 read: reg 105: 0x0 aic32x4 read: reg 106: 0x0 aic32x4 read: reg 107: 0x0 aic32x4 read: reg 108: 0x0 aic32x4 read: reg 109: 0x0 aic32x4 read: reg 110: 0x0 aic32x4 read: reg 111: 0x0 aic32x4 read: reg 112: 0x0 aic32x4 read: reg 113: 0x0 aic32x4 read: reg 114: 0x0 aic32x4 read: reg 115: 0x0 aic32x4 read: reg 116: 0x0 aic32x4 read: reg 117: 0x0 aic32x4 read: reg 118: 0x0 aic32x4 read: reg 119: 0x0 aic32x4 read: reg 120: 0x0 aic32x4 read: reg 121: 0x0 aic32x4 read: reg 122: 0x0 aic32x4 read: reg 123: 0x0 aic32x4 read: reg 124: 0x0 aic32x4 read: reg 125: 0x0 aic32x4 read: reg 126: 0x0 aic32x4 read: reg 127: 0x0
aic32x4 read: reg 0: 0x0 aic32x4 read: reg 1: 0x0 aic32x4 read: reg 2: 0x60 aic32x4 read: reg 3: 0x0 aic32x4 read: reg 4: 0x3 aic32x4 read: reg 5: 0x91 aic32x4 read: reg 6: 0x7 aic32x4 read: reg 7: 0x14 aic32x4 read: reg 8: 0x90 aic32x4 read: reg 9: 0x0 aic32x4 read: reg 10: 0x0 aic32x4 read: reg 11: 0x82 aic32x4 read: reg 12: 0x88 aic32x4 read: reg 13: 0x0 aic32x4 read: reg 14: 0x80 aic32x4 read: reg 15: 0x2 aic32x4 read: reg 16: 0x0 aic32x4 read: reg 17: 0x8 aic32x4 read: reg 18: 0x82 aic32x4 read: reg 19: 0x88 aic32x4 read: reg 20: 0x80 aic32x4 read: reg 21: 0x1 aic32x4 read: reg 22: 0x0 aic32x4 read: reg 23: 0x4 aic32x4 read: reg 24: 0x0 aic32x4 read: reg 25: 0x0 aic32x4 read: reg 26: 0x1 aic32x4 read: reg 27: 0x0 aic32x4 read: reg 28: 0x0 aic32x4 read: reg 29: 0x1 aic32x4 read: reg 30: 0x84 aic32x4 read: reg 31: 0x0 aic32x4 read: reg 32: 0x0 aic32x4 read: reg 33: 0x0 aic32x4 read: reg 34: 0x0 aic32x4 read: reg 35: 0x0 aic32x4 read: reg 36: 0xcc aic32x4 read: reg 37: 0xee aic32x4 read: reg 38: 0x11 aic32x4 read: reg 39: 0x0 aic32x4 read: reg 40: 0x0 aic32x4 read: reg 41: 0x0 aic32x4 read: reg 42: 0xe aic32x4 read: reg 43: 0x0 aic32x4 read: reg 44: 0x0 aic32x4 read: reg 45: 0x0 aic32x4 read: reg 46: 0x0 aic32x4 read: reg 47: 0x0 aic32x4 read: reg 48: 0x0 aic32x4 read: reg 49: 0x0 aic32x4 read: reg 50: 0x0 aic32x4 read: reg 51: 0x0 aic32x4 read: reg 52: 0x0 aic32x4 read: reg 53: 0x12 aic32x4 read: reg 54: 0x3 aic32x4 read: reg 55: 0x2 aic32x4 read: reg 56: 0x2 aic32x4 read: reg 57: 0x0 aic32x4 read: reg 58: 0x0 aic32x4 read: reg 59: 0x0 aic32x4 read: reg 60: 0x1 aic32x4 read: reg 61: 0x1 aic32x4 read: reg 62: 0x0 aic32x4 read: reg 63: 0xd4 aic32x4 read: reg 64: 0x0 aic32x4 read: reg 65: 0xf7 aic32x4 read: reg 66: 0xf7 aic32x4 read: reg 67: 0x0 aic32x4 read: reg 68: 0x6f aic32x4 read: reg 69: 0x38 aic32x4 read: reg 70: 0x0 aic32x4 read: reg 71: 0x0 aic32x4 read: reg 72: 0x0 aic32x4 read: reg 73: 0x0 aic32x4 read: reg 74: 0x0 aic32x4 read: reg 75: 0xee aic32x4 read: reg 76: 0x10 aic32x4 read: reg 77: 0xd8 aic32x4 read: reg 78: 0x7e aic32x4 read: reg 79: 0xe3 aic32x4 read: reg 80: 0x0 aic32x4 read: reg 81: 0xc0 aic32x4 read: reg 82: 0x44 aic32x4 read: reg 83: 0x13 aic32x4 read: reg 84: 0x13 aic32x4 read: reg 85: 0x0 aic32x4 read: reg 86: 0x0 aic32x4 read: reg 87: 0x0 aic32x4 read: reg 88: 0x7f aic32x4 read: reg 89: 0x0 aic32x4 read: reg 90: 0x0 aic32x4 read: reg 91: 0x0 aic32x4 read: reg 92: 0x0 aic32x4 read: reg 93: 0x0 aic32x4 read: reg 94: 0x0 aic32x4 read: reg 95: 0x0 aic32x4 read: reg 96: 0x7f aic32x4 read: reg 97: 0x0 aic32x4 read: reg 98: 0x0 aic32x4 read: reg 99: 0x0 aic32x4 read: reg 100: 0x0 aic32x4 read: reg 101: 0x0 aic32x4 read: reg 102: 0x0 aic32x4 read: reg 103: 0x0 aic32x4 read: reg 104: 0x0 aic32x4 read: reg 105: 0x0 aic32x4 read: reg 106: 0x0 aic32x4 read: reg 107: 0x0 aic32x4 read: reg 108: 0x0 aic32x4 read: reg 109: 0x0 aic32x4 read: reg 110: 0x0 aic32x4 read: reg 111: 0x0 aic32x4 read: reg 112: 0x0 aic32x4 read: reg 113: 0x0 aic32x4 read: reg 114: 0x0 aic32x4 read: reg 115: 0x0 aic32x4 read: reg 116: 0x0 aic32x4 read: reg 117: 0x0 aic32x4 read: reg 118: 0x0 aic32x4 read: reg 119: 0x0 aic32x4 read: reg 120: 0x0 aic32x4 read: reg 121: 0x0 aic32x4 read: reg 122: 0x0 aic32x4 read: reg 123: 0x0 aic32x4 read: reg 124: 0x0 aic32x4 read: reg 125: 0x0 aic32x4 read: reg 126: 0x0 aic32x4 read: reg 127: 0x0
Best regards
Kailyn
Hi Kailyn,
The cap and the load forms a high pass filter with cutoff fc = 1/(2*pi*R*C). That is the reason you are seeing attenuation of the lower frequencies.
You can increase the Cap to reduce the cutoff. If you remove the cap and measure it on an AP (or some other equipment) with the dc you will not see any low frequency attenuation.
Best Regards.
