Hello Champs,
My customer is urgently asking about layout recommendation for TPA6132A2. I found below descriptions in datasheet, but it would be helpful if I can be informed of other recommendations.
- Use good low equivalent-series-resistance (ESR) ceramic capacitors (X5R material or better is required for best performance).
- Place a 2.2 mF capacitor within 5 mm of the VDD pin. Reducing the distance between the decoupling capacitor and VDD minimizes parasitic inductance and resistance, improving TPA6132A2 supply rejection performance.
- Use 0402 or smaller size capacitors if possible.
- Solder the exposed metal pad on the TPA6132A2RTE QFN package to the landing pad on the PCB. Connect the landing pad to ground or leave it electrically unconnected (floating). Do not connect the landing pad to VDD or to any other power supply voltage.
- The SGND pin is an input reference and must be connected to the headphone ground connector pin. This ensures no turn-on pop and minimizes output offset voltage. Do not connect more than ±0.3 V to SGND.
- PGND is a power ground. Connect supply decoupling capacitors for VDD, HPVDD, and HPVSS to PGND.
- Connect the supply voltage to the VDD pin and decouple it with an X5R or better capacitor.
- Connect the HPVDD pin only to a 2.2 mF, X5R or better, capacitor. Do not connect HPVDD to an external voltage supply. Place both capacitors within 5 mm of their associated pins on the TPA6132A2.
- Ensure that the ground connection of each of the capacitors has a minimum length return path to the device. Failure to properly decouple the TPA6132A2 may degrade audio or EMC performance.
Are there any other layout recommendations?
Best regards,
Kojima
