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TLV320AIC34: Codec frequency configuration

Connie Lu1
Intellectual 2130 points
Part Number: TLV320AIC34


Hi experts,

My customer have some questions regarding TLV320AIC34 on selecting the right MCLK for ADC/DAC codec frequency in order to have a proper operation. They have 2 options listed below to choose from:

  1. Using MCLK of 12.288MHz (PLL is disabled - by pass PLL). This is the simplest design

The fS(ref) = CLKDIV_IN / (128 × Q); where FS(ref)= 48kHz; Q=2(default) then CLKDIV_IN = 48kHz*256=12.288MHz

 

  1. Using existing MCLK of 18.432MHz and enable PLL to achieve proper codec clock frequency without error. What would be correct PLL settings or is this even achievable?

 

With your expertise, what would you recommend between option 1 and 2?

What advantages are there between PLL disable and enable?

Thank you!

Connie

  • 0
    TI__Mastermind 22950 points

    Hi Connie,

    The recommendation really depends on the customer's needs/system. Option 1 would be the simplest implementation and would save some power as the PLL would not need to be on. 

    Option 2 would be recommended only if the MCLK is not an integer multiple of the sampling rate and to help reduce clock jitter. For ease of use and power consumption savings, I would personally go with Option 1. 

    If Option 2 is decided by customer, then the following PLL coefficients can be used for an 18.432MHz MCLK and 48kHz Fs:

    P = 3

    R = 1

    J = 16

    D = 0

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    TI__Intellectual 2130 points

    Hi Aaron,

    Thank you!

    Regards,

    Connie

  • 0 in reply to Connie Lu1
    TI__Intellectual 2130 points

    Hi Aaron,

    In my customer's current architecture, the MCLK of 18.432 is generated by the FPGA and this clock is synchronous to video. So if they use internal PLL(option 2) to generate the codec clock inside the Codec, then they are worried that the audio will not be in sync with video.

    Is option 2 workable for applications where audio and video have to be in sync?

    They use I2S mode transfer and internal to FPGA the BCLK frequency is 2.304MHz. The WCLK is square wave for period(1/48KHz).

    Thanks,

    Connie 

  • 0 in reply to Connie Lu1
    TI__Mastermind 22950 points

    Hello Connie,

    The audio will be synchronous to the MCLK that is provided to the codec and the codec will play the data it's given. So unless the audio and video data gets out of sync elsewhere in the customer's system, I don't see how this would be an issue assuming the CODEC is already configured. 

    Regards,

    Aaron