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PCM1860-Q1: Changes in clock sources and sample rates

Atsushi Hirai
Expert 4070 points
Part Number: PCM1860-Q1
Other Parts Discussed in Thread: PCM1860

Hi team,

I want to know little more detailed procedure of sample rate change.

I'm confused by "Hold clocks for 3 BCK minimum". If I want to change the fs from 48k to 16k in slave mode, should I stop the SCLK and LRCK for 3 BCK period(BCK is not stopped) then activate the new frequency of SCLK, LRCK and BCK?

Please tell me the smartest procedure.

Regards,

  • 0
    TI__Mastermind 23050 points

    Hi Atsushi-san,

    SCLK is actually not required for operation in slave mode. If you are changing sampling rates and keeping the same BCLK you will want to make sure you will still have a sufficient BCKL/FSYNC ratio for the number of channels you are using. In this case then FSYNC should be HiZ for at least 3 BCLK cycles before you apply the new clock. More likely though you would maintain the same ratio and change both FSYNC and BCLK and should wait an appropriate amount of time (~100us) before re-applying the new clocks.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 4070 points

    Kaya-san,

    Thank you for your answer.

    FSYNC means LRCLK, right?

    I thought SCLK is also required because the expected lowest sampling rate is 16kHz or 8kHz.

    I don't want to keep the BCK. If there is no limitation/procedure, I want to change SCLK, BCK and LRCLK at the same time. Is it acceptable?

  • 0 in reply to Atsushi Hirai
    TI__Mastermind 23050 points

    Hi Hirai-san,

    Yes my apologies, if you want to operate at 16kHz it is necessary to provide an MCLK as shown. All of the clocks can change, but I would recommend a slight delay between disabling the clocks and reapplying the new ones. The device will enter the standby state once it loses the clocks. Since the autodetect feature is not guaranteed to work at 16kHz you would also need to do a manual PLL/clock configuration when switching to 16kHz.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 4070 points

    Zak-san,

    Is it okay that keeping SCLK=24.5760MHz input without interrupt and, change LRCK from 96kHz to 48kHz and BCK from 6.144MHz to 3.072MHz with some interrupt?

    BTW, PCM1860 is hardware controlled device so the PLL cannot be configure by manual. How should I understand above your suggestion?

    Regards,

  • 0 in reply to Atsushi Hirai
    TI__Mastermind 23050 points

    Hey Hirai-san,

    I apologize for the confusion, yes there is no option to manually configure the PLL for the hardware controlled devices in the family. As long as an SCKI is provided then the autodetect clocking feature can function down to 8kHz, so this is not an issue for 16kHz operation. In fact, at least for the device I tested it was not necessary to provide an SCKI at 16kHZ, but I would still recommend doing this since we don't guarantee this operation in the datasheet. The SCKI frequency you mention is sufficiently high enough so that there aren't any issues with the approach you describe. It is okay to leave the SCKI running but it should be synchronous with the incoming BCLK and LRCK.

    For the changes from 96kHz to 48kHz you mention though, an SCKI is not necessary. This is only necessary if you are operating at 16kHz and below.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 4070 points

    Zak-san,

    Sorry for repeating the question. But still I cannot fully understand.

    First of all, my customer is going to input SCLK even if it's not required in some cases because their expected sampling rate is 8k,16k, 24k, 44.1k, 48k and 96k.


    Let me simplified my question.

    What is the grand rule(mandatory requirement) for changing the sampling rate of PCM1860 in slave mode?

    Regards,

  • 0 in reply to Atsushi Hirai
    TI__Mastermind 23050 points

    Hi Hirai-san,

    No problem at all, the documentation for this device is not always clear.

    When changing states though, I do recommend following the sequence outlined in the datasheet:

    For changing from state A to State B::

    • Hold clocks (or HiZ from external) for 3 BCK minimum

    • Change clocks (this means BCK and LRCK)

    • Allow ~100 µs (at least 3 BLKs at 48 kHz) for the device to reconfigure

    • Data ramp back in on zero-crossing ramp

    • Transition to State B complete

    Another thing to keep in mind though is that operation at 8kHz requires an SCKI, and the maximum SCKI allowed is 768*fs, or 6.144MHz, so it is not possible to use the 24.576MHz SCKI mentioned above for all sample rates. I believe it should be acceptable to use 6.144MHz for all sample rates.

    Best,

    Zak