Hello,
My customer has a few questions on capacitors shown in the datasheet. Would you please give me your comments?
1. The layout guide line says this, but would you please tell me the purpose of 10uF tantalum capacitor? An E2E post says it can provide more capacitance in a smaller package, so if they can ensure the actual capacitance value of 10uF even with DC bias impact, can they use ceramic capacitor instead?
10.1.1 VCC and VDD Pins
The digital and analog power supply lines to the PCM1802 must be bypassed to the corresponding ground pins
with 0.1-μF ceramic and 10-μF tantalum capacitors as close to the pins as possible to maximize the dynamic
performance of the ADC.
2. The AC coupling capacitor in the datasheet says 8Hz cutoff frequency, but is it really 8Hz? Would you please tell me the reason why it is 8Hz? Or is it a typo and actually 8kHz? What would happen if they add equal or higher capacitor than 1uF to lower the cut off frequency?
Does a higher full-scale input here mean > 0.6*Vcc(Vpp)?
10.1.3 VIN Pins
TI recommends a 1-μF capacitor for AC-coupling, which gives an 8-Hz cutoff frequency. A higher full-scale input
voltage, if required, can be accommodated by adding only one series resistor to each VIN pin.
3. Would you please tell me the reason why it recommends electrolytic capacitor of 10uF here? Can they use 10uF ceramic capacitor instead if they ensure 10uF with DC bias impact?
10.1.4 VREF1 Pin
TI recommends a ceramic capacitor of 0.1 μF and an electrolytic capacitor of 10 μF between VREF1 and AGND
to ensure low source impedance for the ADC references. These capacitors must be placed as close as possible
to the VREF1 pin to reduce dynamic errors on the ADC references.
4. The same goes here on VREF2 pin. Would you please tell me the reason why it recommends electrolytic capacitor of 10uF here? Can they use 10uF ceramic capacitor instead if they ensure 10uF with DC bias impact?
10.1.5 VREF2 Pin
The differential voltage between VREF2 and AGND sets the analog input full-scale range. TI recommends a
ceramic capacitor of 0.1 μF and an electrolytic capacitor of 10 μF between VREF2 and AGND with the insertion
of a 1-kΩ resistor between VCC and VREF2 when using a noisy analog power supply. These capacitors and
resistor are not required for a clean analog supply. These capacitors must be placed as close as possible to the
VREF2 pin to reduce dynamic errors on the ADC references. Full-scale input level is affected by this 1-kΩ
resistor, decreasing by 3%.
Best Regards,
Yoshikazu Kawasaki
