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PCM3168A: The quality of SCKI

user252459
Prodigy 20 points
Part Number: PCM3168A
Other Parts Discussed in Thread: PCM3168

We found the description in the datatsheet as below.

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12.1.10 System Clock and Audio Interface Clocks
The quality of SCKI may influence dynamic performance, because the PCM3168A device (both the ADC and
DAC) operates based on SCKI. Therefore, it may be required to consider the jitter, duty, and rise and fall time of
the system clock.

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However, we cannot find the requirement values, Jitter, rise and fall time of the system clock in the datasheet.

Please let us know that values? We need its Maxmum value.

  • 0
    TI__Guru 64205 points

    Hello,

    The PCM3168 does not use an internal PLL and operates with dedicated internal dividers that will be nearly directly affected by SCKI jitter.  Therefore jitter-in = jitter-out and it will be somewhat up to your performance metrics what can be tolerated.

    If the jitter is very very large then it's possible for the conditions listed below from Datasheet Section 9.4.5 to occur:

    If the relationship between SCKI and LRCKDA changes more than ±2 BCKDA clocks because of jitter, sampling frequency change, and so forth, the DAC internal operation halts within 1 / fS, and the analog output is forced into VCOMDA (0.5 VCCDA1) until re-synchronization between SCKI, LRCKDA, and BCKDA is completed and then tDACDLY3 passes. If the relationship between SCKI and LRCKAD changes more than ±2 BCKADs because of jitter, sampling frequency change, and so forth, the ADC internal operation halts within 1 / fS, and the digital output is forced into a 0 code until re-synchronization between SCKI, LRCKAD, and BCKAD is completed and then tADCDLY3 passes. In the event the change is less than ±2 BCKAD/DAs, re-synchronization does not occur, and this analog/digital output control and discontinuity do not occur