TLV320ADC3101: Channel Offset Setting for I2S Mode

Sadanori Kato

Part Number: TLV320ADC3101
Other Parts Discussed in Thread: TLV320ADC3100

Hi,

For I2S mode, the timing chart is mentioned on page 19 of TLV320ADC3101 data sheet. So, it seems that Ch_Offset_1 is set to "1" in this figure. Is my understanding correct?

If Ch_Offset_1 is set to "0", the following figure should be correct.

Best regards,
Kato

over 4 years ago

0 Zak Kaye over 4 years ago

TI__Mastermind 23050 points

Hi Kato-san,

The I2S protocol actually includes a 1 BCLK cycle delay between the FSYNC edge and the start of data, so there is an offset of 1 inherent to the protocol. Therefore, the first diagram above is the correct one with an offset of 0 because any offset added in the offset register is in addition to the standard format for the selected protocol.

Best,

Zak

0 Sadanori Kato over 4 years ago in reply to Zak Kaye

Guru 36540 points

Hi Zak-san,

Thank you for your reply.

The second figure is mentioned on page 18 of TLV320ADC3100 data sheet. Strictly speaking, is that timing chart incorrect?

Best regards,
Kato

0 Zak Kaye over 4 years ago in reply to Sadanori Kato

TI__Mastermind 23050 points

Hi Kato-san,

It seems there is an error in the diagram for TLV320ADC3100. Notice that the description of the I2S protocol, "MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock" is not accurately reflected in the second diagram.

Thanks for catching this!

Best,

Zak

0 Sadanori Kato over 4 years ago in reply to Zak Kaye

Guru 36540 points

Hi Zak-san,

Thank you for the information.

I understand.

Best regards,
Kato

Audio

Audio forum

TLV320ADC3101: Channel Offset Setting for I2S Mode