PCM4220: Clock Requirements

Hideki Hayashi1

Expert 8710 points

Part Number: PCM4220
Other Parts Discussed in Thread: TLV320ADC6140

Hello Team,

I have some questions about clock requirements. Could you please answer below.

1, Is there any timing requirements on MCKI compared with BCK when MCKI is 256fs in normal mode?

2, To consider some delay between BCK and LRCK, how long can delay be accepted? (like ~ns?)

3, Which clock is tDO in figure 1 defined as delay against : LRCK or BCK ?

4, Do you have any data or graph about something (THD+N, dynamic range, ...) vs jitter? This is because there are description "For best performance, the master clock jitter should be maintained below 40ps peak amplitude.". And customer concern how worse if using clock over 40ps jitter.

Best regards,

Hideki

over 4 years ago

0 Zak Kaye over 4 years ago

TI__Mastermind 23050 points

Hi Hayashi-san,

I unfortunately don't have more detailed info on the timing requirements of this device but all of the clocks need to be synchronous. Thus if you are using the device in slave mode it is recommended that the master device share the same MCLK as PCM4220 so that all the clocks will be aligned.

The tDO spec is referenced to the BCK edge.

I don't have any performance data with higher than recommended jitter, but given that the device does not integrate a PLL I would expect it to be sensitive to this clock jitter and would try to minimize this. PCM4220 is our highest performance family of ADCs so I would recommend following all datasheet guidelines to guarantee this performance. Otherwise TLV320ADC6140 may be a good device to consider as it can achieve similar levels of performance with a DRE algorithm and also integrates a PLL so it is less sensitive to jitter.

Best,

Zak

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PCM4220: Clock Requirements