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TLV320ADC3140: tlv320adc3140 synchronization shift between PDM mics 7 and 8 compared to other mics

Ahmed Abdelgaber
Prodigy 70 points
Part Number: TLV320ADC3140


Hello,

I am using a couple of tlv320adc3140 codecs with one as a master and the second as a slave, each codec is connected to 8 PDM mics with the 4 input pins, each pair is connected to one input pin.

the mics is arranged in a circle with 45 deg separated between each 2 pairs. 

I managed to have a sound source between mics 1 and 8 and I was expecting that the wav channels of these mics should be synced as the distance between these mics and the source is almost the same.

The result was that there is a shift between them with almost 6 elements.

I am configuring the codec to work on rate of 48khz and I am getting the same difference (the 6 elements shift) when working on the 16khz rate.

I even used the CH8_CFG4 register to adjust this shift but the max value that I can set is 255 which corresponds to 2 sampling indices while I need 6.

I am looking for any help to figure out the root cause of this issue and how I can fix this shift.

please let me know if any more details is needed to clarify the issue.

Thanks in advance for your valued input.

Best regards,

Ahmed 

  • 0
    TI__Mastermind 23050 points

    Hi Ahmed,

    Do you have a diagram of your system that you could share so we can better understand your setup and the configuration and distance of your mic array? 

    When you say elements do you mean samples? 6 samples would be a much larger delay between channels than would ever be expected. Are you comparing mic channels in the same array, or between the arrays of different devices? i.e. are the mics you are comparing being driven from the same PDMCLK?

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 70 points

    Hello Zak,

    my system contains of 2 TLV320ADC3140 codecs, each codec is connected to 8 mics and one of them is configured as master and the other is configured as a slave, each mics pair is connected to the same data and PDM clk pins.

    The distance between mics is about 3 cm (I mean the distance between mic 1 and mic 8 which should have no shift as the sound source is locating in the same distance between them) 

    For simplicity we can ignore the slave codec and its mics (taking into consideration that the same shift for the same mics exists for the slave codec as well).

    I am also attaching the register configuration values for the master codec.

    For the shift, yes I mean samples.

    For the compared mics, yes , I am comparing the mics connected to the same codec device and suppository this means they are sharing the same PDMCLK however the PDMCLK output pins are different (GPO0 is used as PDMCLK for mics 1 and 2 pair and GPO3 is used as PDMCLK for mics 7 and 8 pair).

    hope this clarifies the issue.

    Fullscreen 5123.reg_values.txt Download 
    reg 0x02 = 0x01 #SLEEP_CFG
reg 0x07 = 0x30 #ASI_CFG0
reg 0x13 = 0x87 #MST_CFG0
reg 0x14 = 0x48 #MST_CFG1
reg 0x16 = 0x98 #CLK_SRC
reg 0x21 = 0xA2 #GPIO_CFG0
reg 0x22 = 0x41 #GPO_CFG0 
reg 0x23 = 0x41 #GPO_CFG1
reg 0x24 = 0x41 #GPO_CFG2
reg 0x25 = 0x41 #GPO_CFG3
reg 0x2B = 0x45 #GPI_CFG0
reg 0x2C = 0x67 #GPI_CFG1
reg 0x3C = 0x40 #CH1_CFG0
reg 0x41 = 0x40 #CH2_CFG0
reg 0x46 = 0x40 #CH3_CFG0
reg 0x4B = 0x40 #CH4_CFG0
reg 0x73 = 0xFF #IN_CH_EN
reg 0x74 = 0xFF #OUT_CH_EN
reg 0x6C = 0x40 #DSP_CFG1
reg 0x75 = 0x60 #PWR_CFG

  • 0 in reply to Ahmed Abdelgaber
    Prodigy 70 points

    Hello Zak,

    is there any update about this issue?

    Please let me know if you need any more information to clarify this issue.

    Best regards,

    Ahmed 

  • 0 in reply to Ahmed Abdelgaber
    TI__Mastermind 23050 points

    Hey Ahmed,

    I am not sure why you would be experiencing delay this large between microphones. Have you tested other pairs of microphones in your array and seen similar results or is it only with these two channels? Are you certain the polarity of the mics sharing input pins has been configured correctly?

    I would also recommend looking through this app note on the processing blocks supported in various conditions and making sure that you aren't operating the device outside of its supported range: 

    It may also be helpful to read page 1 register 0x06. If this register returns a value of 0x11 then the configuration you are using is not supported. If it returns 0x10 then there shouldn't be a proplem.

    Best,

    Zak

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 70 points

    Hello Zak,

    Thanks a lot for your help.

    actually I checked register #0x06 in page #1 and the returned value was 0x10.

    We still faces the same issue.

    as a work around, we resync the channels frames in our SW part.

    So you think there is something more to do for that issue or I should close it?

    Thanks and regards,

    Ahmed 

  • +1 in reply to Ahmed Abdelgaber
    TI__Mastermind 23050 points

    Hi Ahmed, 

    I still don't fully understand the issue you were facing but it sounds like perhaps it is just a slot alignment issue? The data slotting of the device is very flexible. If both devices are running synchronously along with the PDM clocks then I don't see why it would be necessary to resync the frames, but if this is a viable solution in your system then we can close the issue.

    Best,

    Zak