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TLV320AIC3256EVM-U: Interface PDM mems microphone with 3256 EVM-U

Santhosh Ravisankar
Prodigy 155 points
Part Number: TLV320AIC3256EVM-U

Hi,

I have been working on design to interface a digital microphone to the 3256 codec. I am currently using PurePath Studio to achieve this. I have successfully interfaced an analog microphone and played back recordings from it. However, I am having issues with the digital microphone. As per the reference manual, I am using SCLK as my digital mic input and MISO as clock for the digital mic. I have the playback registers configured as well. I am able to see output from the D-mic's DATA and there seems to be output from the codec i2s DOUT as well. I am unable to hear any playback. Could you please help me in case I am missing something here? I have shared the related register settings and sample output screenshot below.

Note: I am sampling at 32kHz. 

;-----------------------------------------------------------------------------------

; ADC Channel Configuration

;-----------------------------------------------------------------------------------

reg[  1][ 51] = 0x68; Mic Bias enabled

reg[  1][ 52] = 0x00; Route IN3L to LEFT_P with 10K input impedance /off for now

reg[  1][ 54] = 0x00; Route CM1L to LEFT_M with 10K input impedance //off for now

reg[  1][ 55] = 0x00 ; Route IN3R to RIGHT_P with 10K input impedance //off for now

reg[  1][ 57] = 0x00 ; Route CM1R to RIGHT_M with 10K input impedance //off for now

reg[  1][ 59] = 0x28; Enable MicPGA_L Gain Control, 0dB //SHOULD BE 0 0

reg[  0][ 81] = 0xD4; Power up LADC/RADC

reg[  0][ 82] = 0x00; Unmute LADC/RADC

reg[  0][ 83] = 0x18; left  mic 12db vol

reg[  0][ 84] = 0x18; right mic 12db vol

reg[  0][ 55] = 0x0E; miso dmic clock

reg[  0][ 56] = 0x02; SCLK

;-----------------------------------------------------------------------------------

; DAC Channel Configuration

;-----------------------------------------------------------------------------------

reg[  1][ 12] = 0x08 ; Route LDAC to HPL

reg[  1][ 13] = 0x08 ; Route RDAC to HPR

reg[  1][ 14] = 0x09 ; Route LDAC to LOL

reg[  1][ 15] = 0x08 ; Route LDAC to LOR

reg[  0][ 63] = 0xD6 ; Power up LDAC/RDAC w/ soft stepping

reg[  1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain

reg[  1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain

reg[  1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain

reg[  1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain

reg[  1][  9] = 0x3C ; Power down HPL/HPR and LOL/LOR drivers, MAL/MAR

reg[  0][ 64] = 0x01 ; left output volume controlled by right channel vol

reg[  0][ 66] = 0x14 ; dac vol

reg[  0][ 67] = 0x80;  headset detection

  • 0
    TI__Expert 6440 points

    Hi Santhosh,

    How are you setting up the signal flow for your playback path? Are you using a PPS process flow to route the Decimator (Dec4x) data through the InterDSP component to the Interpolator (Int8x) component? Or are you playing the playback data from the PC through the USB controller? Let us know which path is having the problem.

    Diljith

  • 0 in reply to Diljith
    Prodigy 155 points

    Hi Diljith,

    For this design I am using a PPS process flow to route the decimator through interDSP component to the interpolator. This is the path that I am having a problem with. 

    Best,

    Santhosh

  • 0 in reply to Santhosh Ravisankar
    TI__Expert 6440 points

    Hi Santosh,

    Please share (email if you prefer) the flow with us.  Are you using the EVM clocks or external clock?

    Best Regards.

  • 0 in reply to Diljith
    Prodigy 155 points

    Hi Diljith,

    I am using the EVM clocks and default settings for the pll divider values,mdac,ndac to have 32 kHz sample rate.  I have shared the flow over email. Please let me know if you require more information.

    Best,
    Santhosh

  • 0 in reply to Santhosh Ravisankar
    TI__Expert 6440 points

    I checked all the analog outputs and the configuration registers are enabling and powering them. So, let us check the Mic. and ADC data.

    Could you please record the ADC output using Audacity and check that the recorded waveform is proper?

    You can also put a tone generator in the process flow and route it to the Interpolator to make sure that the Analog outputs are working properly.

    Diljith

  • 0 in reply to Diljith
    Prodigy 155 points

    Hi Diljith,

    The analog outputs are working properly since I am able to hear the tone from the generator.

    I am not exactly sure how I can check the ADC output from PPS directly. 

    One additional question : If my digital mic is configured for the right ADC channel, should I be using a decimating stereo input's right channel?

    Best,

    Santhosh

  • 0 in reply to Santhosh Ravisankar
    TI__Expert 6440 points

    Hi Santhosh,

    Thanks for confirming that analog outputs are working fine. It might be the case, as you suspect, that the left and right channels are interchanged.

    For digital mic configured for right channel, a stereo decimator has to be used and the right output has to be routed to other components for further processing.

    The decimator output can be routed to I2S Out component for checking ADC channel. The I2S Out component will send the data on the I2S bus to the USB controller of the EVM which can then be recorded on the PC.

    Diljith

  • 0 in reply to Diljith
    Prodigy 155 points

    Hi Diljith,

    I did try using a stereo decimator then using the right output for further processing. I still cannot hear audio.

    That being said I tried recording the right stereo decimator, nothing was recorded. Are you suspecting that the mic might be an issue?

    When I view the data line directly on the scope without connecting it to SCLK, I see a lot of data pulses. (could be noise)

    However when  I connect the digital mic data line to SCLK, I do not see anything on the scope.

    Best,

    Santhosh

  • 0 in reply to Santhosh Ravisankar
    TI__Expert 6440 points

    Hi Santhosh,

    Could you check the specs of the digital mic? The dig mic is being clocked with a 4 MHz clock. The mic may not support such a high clock.

    You can reduce the ADC OSR from 128 to 64 to reduce the clock to 2 MHz. That would also need a change to the MADC from 12 to 24.

    You can refer to the changes below (highlighted in yellow). I have also changed the routing of the dig mic to left channel to make it work with a mono decimator.

    Best Regards.

  • 0 in reply to Diljith
    Prodigy 155 points

    Hello Diljith, 

    I had tried the above solutions and it still did not yield any results. But as you have suspected, it might be the digital mic issue.

    Thanks,

    Santhosh