TLV320ADC3140: How to use PLL in slave mode

Hello Kato-san,

The easiest mode to use the device in will enable the "AUTO_CLK_CFG" mode which will automatically use the PLL to detect the desired mode of operation from the incoming BCLK and WCLK signals.  To save power, or to use specific settings the Auto clock configuration can be disabled and so can the PLL.  Here is a snippet from a few datasheet sections that describe this in more detail which also explains some of the caveats when not using the PLL.

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC modulator and digital filter engine, as well as other control blocks.  The device also supports an option to use BCLK, GPIO1, or the GPIx pin (as MCLK) as the audio clock source without using the PLL to reduce power consumption. However, the ADC performance may degrade based on jitter from the external clock source, and some processing features may not be supported if the external audio clock source frequency is not high enough. Therefore, TI recommends using the PLL for high-performance applications. More details and information on how to configure and use the device in low-power mode without using the PLL are discussed in the TLV320ADCx140 Operation for Low-Power Critical Applications application report.

7 DIS_PLL_SLV_CLK_SRC R/W 0h Audio root clock source setting when the device is configured with the PLL disabled in the auto clock configuration for slave mode (AUTO_MODE_PLL_DIS = 1). 0d = BCLK is used as the audio root clock source 1d = MCLK (GPIO or GPIx) is used as the audio root cloc

Hi Kato,

Yes, you can use the PLL in the TLV320ADC3140 in slave mode.  You need to ensure you power up the PLL by writing to the PWR_CFG register as well (page = 0x00, address = 0x75).