TLV320AIC3204: aic3204 as a slave device, no sound comes out when recoding

Haiwen Huang

Part Number: TLV320AIC3204

Dears:

aic3204 as a slave device, mclk = 12.288M, sampling 48K, connected to In3R / In3L, no sound comes out when recording. Below is the code.
Could you please help check below code or help provide a workable register configuration ?

/* Configure AIC3204 */
aic3204_write(IIC_device_addr[num], 0, 0x0); // Select page 0
aic3204_write(IIC_device_addr[num], 1, 0x1); // Reset Codec
mdelay(20);

aic3204_write(IIC_device_addr[num], 0, 0x1); // Select to page 1
aic3204_write(IIC_device_addr[num], 1, 0x8); // DisabLED weak connection of AVDD with DVDD
aic3204_write(IIC_device_addr[num], 2, 0x1); // Enable analog Blocks, use LDO power (is LDO power being used? If it is, then this register needs to be set correclty to use LDO).

/* PLL and clocks config and Power Up */
// mclk=12.288m, fs=48K, config: p=R=1, j=7, D=0, madc=2, nadc=7, aosr=128
aic3204_write(IIC_device_addr[num], 0, 0x0); // Select page 0
///aic3204_write(IIC_device_addr[num], 27, 0x4d); // BCLK and WCLK is set as output from AIC3204(Master) 00: audio InteRFace = dsp
aic3204_write(IIC_device_addr[num], 27, 0x1); // BCLK and WCLK is set as input AIC3204(slave) 00: audio InteRFace = i2s
aic3204_write(IIC_device_addr[num], 28, 0x0); // Data ofset = 0
aic3204_write(IIC_device_addr[num], 4, 0x3); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
aic3204_write(IIC_device_addr[num], 6, 0x7); // **PLL setting: J=7
aic3204_write(IIC_device_addr[num], 7, 0x0); // PLL setting: HI_BYTE(D)
aic3204_write(IIC_device_addr[num], 8, 0x0); // PLL setting: LO_BYTE(D)
aic3204_write(IIC_device_addr[num], 30, 0x80); // For 32 bit clocks per frame in Master mode ONLY (make sure that BCLK >= [ (# bits per channel) * 2 ]
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
// For 48 KHz sampling
aic3204_write(IIC_device_addr[num], 5, 0x91); // PLL setting: Power up PLL, P=1 and R=1
aic3204_write(IIC_device_addr[num], 13, 0x01); // Hi_Byte(DOSR) for DOSR = 256 decimal or 0x01080 DAC oversamppling
aic3204_write(IIC_device_addr[num], 14, 0x00); // Lo_Byte(DOSR) for DOSR = 256 decimal or 0x0100
aic3204_write(IIC_device_addr[num], 20, 0x00); // AOSR for AOSR = 256 decimal or 0x0000 for decimation filters 1 to 6
aic3204_write(IIC_device_addr[num], 11, 0x87); // Power up NDAC and set NDAC value to 3 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 12, 0x82); // Power up MDAC and set MDAC value to 8 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 18, 0x82); // Power up NADC and set NADC value to 8 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 19, 0x87); // Power up MADC and set MADC value to 6 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 20, 0x80); // AOSR = 128 (default).
aic3204_write(IIC_device_addr[num], 60, 0x19); // Power up PRB_P25 for beep generator Selects the ADC (recording) signal processing block
aic3204_write(IIC_device_addr[num], 61, 0x01); // ADC Singal Processing Block PRB_R1 ADC Signal Processing Block Control Register
aic3204_write(IIC_device_addr[num], 48, 0xff); // Power up MADC and set MADC value to 6 (comments below differ from the values)
aic3204_write(IIC_device_addr[num], 49, 0xff); // Power up PRB_P25 for beep generator

/* DAC ROUTING and Power Up */
aic3204_write(IIC_device_addr[num], 0, 0x01); // Select page 1
aic3204_write(IIC_device_addr[num], 12, 0x08); // LDAC AFIR routed to HPL
aic3204_write(IIC_device_addr[num], 13, 0x08); // RDAC AFIR routed to HPR &&&&&&&
aic3204_write(IIC_device_addr[num], 14, 0x00); // Right Channel DAC reconstruction filter's negative terminal is not routed to LOL
aic3204_write(IIC_device_addr[num], 15, 0x00); // Right Channel DAC reconstruction filter output is not routed to LOR

aic3204_write(IIC_device_addr[num], 0, 0x00); // Select page 0
aic3204_write(IIC_device_addr[num], 64, 0x02); // Left vol=right vol
aic3204_write(IIC_device_addr[num], 65, 0x00); // Left DAC gain to 0dB VOL; Right tracks Left
aic3204_write(IIC_device_addr[num], 66, 0x81); // right mute
aic3204_write(IIC_device_addr[num], 63, 0xd4); // Power up left,right data paths and set channel

aic3204_write(IIC_device_addr[num], 0, 0x01); // Select page 1
aic3204_write(IIC_device_addr[num], 20, 0x69); // Soft Step, De-pop, 6 time constants, 6k ohm.
aic3204_write(IIC_device_addr[num], 16, 0x1d); // Unmute HPL , 29dB gain
aic3204_write(IIC_device_addr[num], 17, 0x3a); // Unmute HPR , -6dB gain
aic3204_write(IIC_device_addr[num], 9, 0x30); // Power up HPL,HPR
aic3204_write(IIC_device_addr[num], 10, 0x33); // HP powered from LDOIN, CM voltage = 1.65V

aic3204_write(IIC_device_addr[num], 0, 0x00); // Select page 0
mdelay(20); // Wait
aic3204_write(IIC_device_addr[num], 16, 15); // Unmute HPL set gain
aic3204_write(IIC_device_addr[num], 17, 00); // Unmute HPR set gain

/* ADC ROUTING and Power Up */
aic3204_write(IIC_device_addr[num], 0, 1 ); // Select page 1
///aic3204_write(IIC_device_addr[num], 52, 0x10 ); //IN2L is routed to Left MICPGA with 40K resistance
///aic3204_write(IIC_device_addr[num], 55, 0x00 ); //IN2R is not routed to Right MICPGA
aic3204_write(IIC_device_addr[num], 52, 0x04); //IN3L is routed to Left MICPGA with 10K resistance
aic3204_write(IIC_device_addr[num], 55, 0x04); //IN3R is not routed to Right MICPGA
aic3204_write(IIC_device_addr[num], 54, 0x03); // CM is routed to Left MICPGA via CM2L with 40K resistance
aic3204_write(IIC_device_addr[num], 57, 0xC0); // CM is routed to right MICPGA via CM2L with 40K resistance
///aic3204_write(IIC_device_addr[num], 59, 0x80); // MIC_PGA_L unmute
///aic3204_write(IIC_device_addr[num], 60, 0x80); // MIC_PGA_R unmute
aic3204_write(IIC_device_addr[num], 59, 0x0C); // MIC_PGA_L unmute
aic3204_write(IIC_device_addr[num], 60, 0x0C); // MIC_PGA_R unmute

aic3204_write(IIC_device_addr[num], 0, 0); // Select page 0
///aic3204_write(IIC_device_addr[num], 81, 0xa0); // Powerup Left and Right ADC
///aic3204_write(IIC_device_addr[num], 82, 0x4); // Unmute Left and Right ADC
aic3204_write(IIC_device_addr[num], 81, 0xC0); // Powerup Left and Right ADC
aic3204_write(IIC_device_addr[num], 82, 0x00); // Unmute Left and Right ADC

over 4 years ago

0 Diljith over 4 years ago

TI__Expert 6440 points

Hi Haiwen,

The register settings are for configuring the Codec in master mode.

Can you measure the WCLK and BCLK signals and check if the frequency is proper?

Best Regards.

0 qing kong over 4 years ago

Prodigy 130 points

Hi Diljith，

firstly, Codec works in slave mode, which register settings is wrong? The follow config lists is the newest settings.

/* Configure AIC3204 */
aic3204_write(IIC_device_addr[num], 0, 0x0); // Select page 0
aic3204_write(IIC_device_addr[num], 1, 0x1); // Reset Codec
mdelay(10);

aic3204_write(IIC_device_addr[num], 60, 0x0C);
aic3204_write(IIC_device_addr[num], 61, 0x04); // ADC Singal Processing Block PRB_R4

/* ADC ROUTING and Power Up */
aic3204_write(IIC_device_addr[num], 0, 1 ); // Select page 1
aic3204_write(IIC_device_addr[num], 2, 0x9);
aic3204_write(IIC_device_addr[num], 1, 0x8); // DisabLED weak connection of AVDD with DVDD
aic3204_write(IIC_device_addr[num], 2, 0x0); // 0x1 Enable analog Blocks, use LDO power (is LDO power being used? If it is, then this register needs to be set correclty to use LDO).
aic3204_write(IIC_device_addr[num], 10, 0x7B); // 0x3B, [6]=1
aic3204_write(IIC_device_addr[num], 61, 0x0); // Select ADC PTM_R4
aic3204_write(IIC_device_addr[num], 3, 0x0); // Select DAC PTM_P3/4
aic3204_write(IIC_device_addr[num], 4, 0x0);
aic3204_write(IIC_device_addr[num], 71, 0x32); // 3.1ms
aic3204_write(IIC_device_addr[num], 123, 0x1); // 3.1ms

aic3204_write(IIC_device_addr[num], 51, 0x40); //Power-up MIC BIAS 0x68
aic3204_write(IIC_device_addr[num], 52, 0x04); //IN3L is routed to Left MICPGA with 10K resistance
aic3204_write(IIC_device_addr[num], 54, 0x40); // CM is routed to Left MICPGA via CM2L with 10K resistance
aic3204_write(IIC_device_addr[num], 55, 0x04); //IN3R is not routed to Right MICPGA
aic3204_write(IIC_device_addr[num], 57, 0x40); // CM is routed to Left MICPGA via CM2L with 10K resistance
aic3204_write(IIC_device_addr[num], 59, 0x0C); // MIC_PGA_L unmute
aic3204_write(IIC_device_addr[num], 60, 0x0C); // MIC_PGA_R unmute

aic3204_write(IIC_device_addr[num], 0, 0); // Select page 0
aic3204_write(IIC_device_addr[num], 81, 0xC0); // Powerup Left and Right ADC
aic3204_write(IIC_device_addr[num], 82, 0x00); // Unmute Left and Right ADC
aic3204_write(IIC_device_addr[num], 83, 0x14); //# Left ADC Channel Volume = 10dB
aic3204_write(IIC_device_addr[num], 84, 0x14); //# Right ADC Channel Volume = 10dB

secondly,

bclk = mclk/8，not get data.

0 qing kong over 4 years ago in reply to qing kong

Prodigy 130 points

more info:

wclk = 48K，bclk=1.5M

0 Diljith over 4 years ago in reply to qing kong

TI__Expert 6440 points

Register configurations appear to be proper. IN3L and IN3R are routed to the Left and Right channels and the clock configurations is set for 48 kHz operation.

Please check if the supplies (LDOIn, AVDD and DVDD) and MICBIAS have the right voltage. Please also check if the I2S clock frequencies are proper.

Best Regards.

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

In3L and In3R is Single-ended connection,

LDOIn = 3.3v

AVDD = 1.7v

DVDD = 1.7v

MICBIAS = 0v, but page1 reg51 value=0x68; 0xa=0x7b;

i2s clock(mclk) 12.288M works fine.

page 0:

0x2: 0x60
0x3: 0x0
0x4: 0x3
0x5: 0x91
0x6: 0x7
0x7: 0x0
0x8: 0x0
0x9: 0x0
0xa: 0x0
0xb: 0x82
0xc: 0x87
0xd: 0x0
0xe: 0x80
0xf: 0x2
0x10: 0x0
0x11: 0x8
0x12: 0x87
0x13: 0x82
0x14: 0x80
0x15: 0x1
0x16: 0x0
0x17: 0x4
0x18: 0x0
0x19: 0x0
0x1a: 0x1
0x1b: 0x1
0x1c: 0x0
0x1d: 0x0
0x1e: 0x88
0x1f: 0x0
0x20: 0x0
0x21: 0x0
0x22: 0x0
0x23: 0x0
0x24: 0x44
0x25: 0x0
0x26: 0x0
0x27: 0x0
0x28: 0x0
0x29: 0x0
0x2a: 0x0
0x2b: 0x0
0x2c: 0x0
0x2d: 0x0
0x2e: 0x0
0x2f: 0x0
0x30: 0x0
0x31: 0x0
0x32: 0x0
0x33: 0x0
0x34: 0x0
0x35: 0x12
0x36: 0x3
0x37: 0x2
0x38: 0x3
0x39: 0x0
0x3a: 0x0
0x3b: 0x0
0x3c: 0xc
0x3d: 0x1
0x3e: 0x0
0x3f: 0x14
0x40: 0xc
0x41: 0x0
0x42: 0x0
0x43: 0x0
0x44: 0x6f
0x45: 0x38
0x46: 0x0
0x47: 0x0
0x48: 0x0
0x49: 0x0
0x4a: 0x0
0x4b: 0xee
0x4c: 0x10
0x4d: 0xd8
0x4e: 0x7e
0x4f: 0xe3
0x50: 0x0
0x51: 0xc0
0x52: 0x0
0x53: 0x14
0x54: 0x14
0x55: 0x0
0x56: 0x0
0x57: 0x0
0x58: 0x7f
0x59: 0x0
0x5a: 0x0
0x5b: 0x0
0x5c: 0x0
0x5d: 0x0
0x5e: 0x0
0x5f: 0x0
0x60: 0x7f
0x61: 0x0
0x62: 0x0
0x63: 0x0
0x64: 0x0
0x65: 0x0
0x66: 0x0
0x67: 0x0
0x68: 0x0
0x69: 0x0
0x6a: 0x0
0x6b: 0x0
0x6c: 0x0
0x6d: 0x0

page1:

0x1: 0x8
0x2: 0x0
0x3: 0x0
0x4: 0x0
0x5: 0x0
0x6: 0x0
0x7: 0x0
0x8: 0x0
0x9: 0x0
0xa: 0x7b
0xb: 0x10
0xc: 0x0
0xd: 0x0
0xe: 0x0
0xf: 0x0
0x10: 0x40
0x11: 0x40
0x12: 0x40
0x13: 0x40
0x14: 0x0
0x15: 0x0
0x16: 0x0
0x17: 0x0
0x18: 0x0
0x19: 0x0
0x1a: 0x0
0x1b: 0x0
0x1c: 0x0
0x1d: 0x0
0x1e: 0x0
0x1f: 0x0
0x20: 0x0
0x21: 0x0
0x22: 0x0
0x23: 0x0
0x24: 0x0
0x25: 0x0
0x26: 0x0
0x27: 0x0
0x28: 0x0
0x29: 0x0
0x2a: 0x0
0x2b: 0x0
0x2c: 0x0
0x2d: 0x0
0x2e: 0x0
0x2f: 0x0
0x30: 0x0
0x31: 0x0
0x32: 0x0
0x33: 0x68
0x34: 0x4
0x35: 0x0
0x36: 0x40
0x37: 0x4
0x38: 0x0
0x39: 0x40
0x3a: 0x0
0x3b: 0xc
0x3c: 0xc
0x3d: 0x0
0x3e: 0x3
0x3f: 0x0
0x40: 0x0
0x41: 0x0
0x42: 0x0
0x43: 0x0
0x44: 0x0
0x45: 0x0
0x46: 0x0
0x47: 0x32
0x48: 0x0
0x49: 0x0
0x4a: 0x0
0x4b: 0x0
0x4c: 0x0
0x4d: 0x0
0x4e: 0x0
0x4f: 0x0
0x50: 0x0
0x51: 0x0
0x52: 0x0
0x53: 0x0
0x54: 0x0
0x55: 0x0
0x56: 0x0
0x57: 0x0
0x58: 0x0
0x59: 0x0
0x5a: 0x0
0x5b: 0x0
0x5c: 0x0
0x5d: 0x0
0x5e: 0x0
0x5f: 0x0
0x60: 0x0
0x61: 0x0
0x62: 0x0
0x63: 0x0
0x64: 0x0
0x65: 0x0
0x66: 0x0
0x67: 0x0
0x68: 0x0
0x69: 0x0
0x6a: 0x0
0x6b: 0x0
0x6c: 0x0
0x6d: 0x0
0x6e: 0x0
0x6f: 0x0
0x70: 0x0
0x71: 0x0
0x72: 0x0
0x73: 0x0
0x74: 0x0
0x75: 0x0
0x76: 0x0
0x77: 0x0
0x78: 0x0
0x79: 0x0
0x7a: 0x0
0x7b: 0x1

0 Diljith over 4 years ago in reply to qing kong

TI__Expert 6440 points

From the ADC flag registers (Page 0, Register 36) it appears that the ADC is powered up and functioning properly. So the problem is either in the input side or output interfaces.

1. Please check the schematic to see if any part of the circuit is driving a low on the micbias pin. Are you writing 0x40 or 0x68 to Page 1, Register 51. Either of these would enable MIC BIAS.

2. On the output side, please measure the WCLK and BCLK frequencies. Do you see any toggling on the DOUT line?

Best Regards

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

page 1 register 51, value is 0x68. and page 1 register 2 , modify the value from 0 to 1, now the micbias=2.32v；

0 qing kong over 4 years ago

Prodigy 130 points

page 1 register 51, value is 0x68. and page 1 register 2 , modify the value from 0 to 1, now the micbias=2.32v, and record works finely.

now, i am debugging playback, including headphone and line outputs, the following list is the register settins, pls help to check, tks.

/* Configure AIC3204 */
aic3204_write(IIC_device_addr[num], 0, 0x0); // Select page 0
aic3204_write(IIC_device_addr[num], 1, 0x1); // Reset Codec
mdelay(10);

aic3204_write(IIC_device_addr[num], 11, 0x82); // Power up NDAC and set NDAC value to 2
aic3204_write(IIC_device_addr[num], 12, 0x87); // Power up MDAC and set MDAC value to 7
aic3204_write(IIC_device_addr[num], 13, 0x00); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x01080 DAC oversamppling
aic3204_write(IIC_device_addr[num], 14, 0x80); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0100
///aic3204_write(IIC_device_addr[num], 30, 0x88); // For 32 bit clocks per frame in Master mode ONLY BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
aic3204_write(IIC_device_addr[num], 60, 0x08); // Set the DAC Mode to PRB_P8

/* ADC ROUTING and Power Up # Configure DAC Channel */
aic3204_write(IIC_device_addr[num], 0, 1 ); // Select page 1
aic3204_write(IIC_device_addr[num], 1, 0x8); // DisabLED weak connection of AVDD with DVDD
aic3204_write(IIC_device_addr[num], 2, 0x0); // 0x1 Enable analog Blocks, use LDO power (is LDO power being used? If it is, then this register needs to be set correclty to use LDO).
aic3204_write(IIC_device_addr[num], 123,0x1); // Set the REF charging time to 40ms
aic3204_write(IIC_device_addr[num], 10, 0x00); // Input Common Mode

aic3204_write(IIC_device_addr[num], 14, 0x25); // De-pop: 5 time constants, 6k resistance
aic3204_write(IIC_device_addr[num], 12, 0x8); // Route LDAC/RDAC to HPL
aic3204_write(IIC_device_addr[num], 13, 0x8); // Route LDAC/RDAC to HPR
aic3204_write(IIC_device_addr[num], 14, 0x8); // Route LDAC/RDAC to LOL
aic3204_write(IIC_device_addr[num], 15, 0x8); // Route LDAC/RDAC to LOR
aic3204_write(IIC_device_addr[num], 9, 0x3c); // Power up HPL/HPR and LOL/LOR drivers

aic3204_write(IIC_device_addr[num], 16, 0x0); // Unmute HPL driver, 0dB Gain
aic3204_write(IIC_device_addr[num], 17, 0x0); // Unmute HPR driver, 0dB Gain

aic3204_write(IIC_device_addr[num], 18, 0x0); // Unmute LOL driver, 0dB Gain
aic3204_write(IIC_device_addr[num], 19, 0x0); // Unmute LOR driver, 0dB Gain

aic3204_write(IIC_device_addr[num], 0, 0); // Select page 0
aic3204_write(IIC_device_addr[num], 65, 0x0); // left DAC digital volume => 0dB
aic3204_write(IIC_device_addr[num], 66, 0x0); // right DAC digital volume => 0dB
aic3204_write(IIC_device_addr[num], 63, 0xd6); // Power up LDAC/RDAC
aic3204_write(IIC_device_addr[num], 64, 0x0); // Unmute LDAC/RDAC

0 Diljith over 4 years ago in reply to qing kong

TI__Expert 6440 points

Are you still facing issues in the playback path?

Best Regards.

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

sorry for reply late, playback now works finely. also, i get a new question, for record path, using In1_R/In1_L， however, the recording contents is a rustling noise. comparing with using In3_L/In3_R， I just modify register[52,54,57,59]. and the following list is my register configs, pls help to check what wrong is it.

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

0 qing kong over 4 years ago in reply to qing kong

Prodigy 130 points

/* ADC ROUTING and Power Up use IN1_L/IN1_R*/
aic3204_write(0, 0x1); // Select page 1
aic3204_write(2, 0x9);
aic3204_write(1, 0x8); // DisabLED weak connection of AVDD with DVDD
aic3204_write(2, 0x1); // 0x1 Enable analog Blocks, use LDO power
aic3204_write(61, 0x0); // power tune Select ADC PTM_R4
aic3204_write(71, 0x32); // analog power up time 6.4ms
aic3204_write(123, 0x1); // reference power up time 40ms

aic3204_write(51, 0x68); // Power-up MIC BIAS 0x68 0x40
aic3204_write(52, 0x80); // IN1L is routed to Left MICPGA with 20K resistance
aic3204_write(54, 0x80); // CM is routed to Left MICPGA via CM1L with 20K resistance
aic3204_write(55, 0x80); // IN1R is not routed to Right MICPGA
aic3204_write(57, 0x80); // CM is routed to right MICPGA via CM1R with 20K resistance
aic3204_write(59, 0x0C); // MIC_PGA_L unmute Gain 6dB
aic3204_write(60, 0x0C); // MIC_PGA_R unmute Gain 6dB

aic3204_write(0, 0); // Select page 0
aic3204_write(61, 0x01); // ADC Singal Processing Block PRB_R1
aic3204_write(81, 0xC0); // Powerup Left and Right ADC
aic3204_write(82, 0x00); // Unmute Left and Right ADC
aic3204_write(83, 0x14); // Left ADC Channel Volume = 10dB
aic3204_write(84, 0x14); // Right ADC Channel Volume = 10dB

Best Regards.

0 Diljith over 4 years ago in reply to qing kong

TI__Expert 6440 points

Hi Qing,

The configuration looks proper. Please do send across the IN1L/IN1R recording and the IN3L/IN3R recording. What are you using as the ADC input - microphone or a line input signal? Is it the same for both IN1 path as well as for the IN3 path?

Best Regards

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

Hi Diljith,

IN3 and IN1 both are using line input signal. also, has the same path. IN1/IN3 has the same PLL configs.

and now in1 recording has not voice.

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

Diljith:

could I have your email ? I can't insert .pcm document as it's too large.

in1.pcm and in3.pcm are respectively configured in1/in3 to input recording data. In1 is all noise, but when measuring with an oscilloscope, the waveform changes with the sound.

0 Diljith over 4 years ago in reply to qing kong

TI__Expert 6440 points

Thanks for sending the recordings. I shall get back to you after analysis.

Best Regards.

0 qing kong over 4 years ago in reply to Diljith

Prodigy 130 points

Hi, Diljith

How's it going? Did you find anything works wrong?

0 qing kong over 4 years ago in reply to qing kong

Prodigy 130 points

Hi diljith:

in1.0326.pcm file has sended to you by email.

I have done new recording test, "in1.0326.pcm" is the recording files. also, I found the problem:

test 1: In1L routed to HPL, In1R routed to HPR， and headphone output works finely.

test 2: recording, speaking out and pressing earplugs, and the recording file is no sound of speech, just the sound of pressing the earplugs.

pls help to check.

Best Regards.

0 Diljith over 4 years ago in reply to qing kong

TI__Expert 6440 points

Based on your off-forum reply that the issue was related to incorrect MONO PCM configuration, I shall mark this issue as closed.

Best Regards.

Audio

Audio forum

TLV320AIC3204: aic3204 as a slave device, no sound comes out when recoding