Hi,
I am working with AIC3254, using the PLL to generate a clock signal on BCLK pin:
At start up, I configure and power up the PLL to generate CODEC_CLKIN, leaving NDAC/NADC/MDAC/MADC powered down. I also configure and power up the BCLK divider.
The first time I power up NDAC to generate DAC_CLK and feed the BCLK divider, I see that the clock signal at BCLK is generated after around 50ms.
Then, I power down NDAC, which makes the clock signal not be generated (that is correct).
The point is that, when I power up NDAC a second time, the clock signal at BCLK is generated almost immediately.
So, my questions are, why is there such difference in the delay of BCLK after power up of NDAC? Should I force a power up and down cycle at start up?
Regards,
Miguel