Hello,
We are working on a design with this device, and have come up with a couple questions during the process:
- Are tantalum capacitors still recommended for this device, or are ceramic acceptable? (All capacitors >1uF are recommended to be tantalum, though this is an older product and may be a dated recommendation)
- We are going to be operating at 48kHz sampling rate with a targeted 12.2880MHz SYSCLK provided with a 256fs divider. What is the tolerance on SYSCLK for the device to operate 48kHz / 256fs? (None appears to be provided in the datasheet, and exactly 12.2880 is impractical)
- Power-On reset: Datasheet states 3 Clock cycles must be complete prior to Vdd > 2.2V. This implies that if Vdd sequencing cannot be controlled by the master, the poweron reset timing cannot be met. If this is the case, is an external reset procedure required on poweron?
- Section "System Clock" states the following:
- "When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) also must be supplied simultaneously. Failure to supply the audio clocks results in a power-dissipation increase of up to three times normal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded"
- Which power supply is this in reference to? (Just Vdd, or VCC1/2?)
- Do these lines simply need to be high as the supply comes up (such as through a pullup), or do they need to actively be applying clock pulses to prevent this high (possibly damaging) power dissipation?
Thank you
