TLV320AIC3101:32kHz sampling set error 0%

Hello Kazuhide,

The PLL settings above will violate some PLL constraints when D ≠ 0000. Please see these constraints below:

I recommend using the PLL settings below. They are taken from the data sheet table 1:

P = 1

R = 1

J = 8

D = 1920

Using these PLL setting will generate an Fs(ref) = 48kHz. This is just a reference sample rate and in order to get an Fs of 32kHz, you will need to set Page 0, Register 2 to 0x11. This will divide 48khz/1.5 to get a 32kHz sample rate. 

Regards,

Aaron Estrada

Hi Aaron,

Thank you for your reply.
I actually tried it and confirmed it.

Thank you.

Kazuhide Nagamoto

Hi Kazuhide,

Great to hear. I will now close this thread. 

Regards,

Aaron Estrada