TAS6422E-Q1: PBTL Issue Schematic Review

Hi Gregg,

I'm sorry for the late reply due to the customer's business trip.

The customer's register setting.

The rest are using registers as default.

MCLK : 12.288mhz

We checked Global Faults 1.

Currently, we checked Clock fault detected.

value of 0x11 is 0x10.

Please guide us on how to improve the register setting.

If they are getting a clock error, then the clocks are not correct.  I see they are using TDM mode, 48kHz Fs, 24 or 32 bit slot, with I2S format.

You should have MCLK=SCLK=12.288MHz, FSync must be 48kHz.  If you have 24Bit data you will need to pad 8 bits at the end.

Hi Gregg,

We tested with feedback comments, but the audio output did not work.

Audio output succeeded if INPUT SAMPLING RATE was changed to 44.1khz during additional test.

Please check if the INPUT SAMPLING RATE 44.1khz setting is normal.

I would appreciate it if you could explain why we should set it to 44.1khz.

Input source :

MCLK = SCLK : 12.288mhz

FSYNC : 48khz

Audio data word : 24 bit

Something must not be quite right with the MCLK, SCLK. and FSYNC.  Please send an oscilloscope screenshot showing these waveforms.

Dear Gregg,

Please refer to the attached file.

If there is an additional request, I will check it.

5557.Waveform.zip