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Linux/TAS2553: Audio does not proper.

Expert 1750 points

Replies: 15

Views: 1005

Part Number: TAS2553

Tool/software: Linux

Hello everyone.

We have developed our custom board with AM5718 processor in which we use the TAS2553 codec IC with 8ohm Speaker.

Please check the attached image for the connection of IC with AM5718.

We have done below chnages in dtsi as below.

sound0: sound0 {
                compatible = "simple-audio-card";
                simple-audio-card,name = "TAS2552";
                simple-audio-card,widgets =
                                "Speaker", "Speaker";
                simple-audio-card,routing =
                                 "Speaker", "SPK";
                simple-audio-card,format = "dsp_b";
                simple-audio-card,bitclock-master = <&sound0_master>;
                simple-audio-card,frame-master = <&sound0_master>;
                simple-audio-card,bitclock-inversion;

                simple-audio-card,cpu {
                        sound-dai = <&mcasp3>;
                        system-clock-frequency = <12000000>;
                };

                sound0_master: simple-audio-card,codec {
                        sound-dai = <&tas2552>;
                        system-clock-frequency = <1800000>;
                };
        };

 

&i2c3 {
    status = "okay";
    clock-frequency = <400000>;
    
    tas2552: tas2552@40 {
    #sound-dai-cells = <0>;
    compatible = "ti,tas2552";
    reg = <0x40>;   /*because we have connected ADDR to gound o.w. it will be 0x41 if it is at VDD*/
    vbat-supply = <&vmain>;
    iovdd-supply = <&v3_3d>;
    avdd-supply = <&ldo3_reg>;
    enable-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
    status = "okay";
    };
}

We have modified the pinmux in uboot-spl as below.

{XREF_CLK2, (M0 | PIN_INPUT)}, /* xref_clk0
{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr1.mcasp3_axr1 */

We have added the "clk_id=TAS2552_PLL_CLKIN_1_8_FIXED;" line in "tas2552_set_dai_sysclk" api of tas2552 codec driver to enable the 1.8 Mhz internal oscillator.

Now we are testing the different wav files using below command but sound does not proper.

root@am57xx-evm:~# amixer controls
numid=2,iface=MIXER,name='DIN source'
numid=3,iface=MIXER,name='Input selection'
numid=1,iface=MIXER,name='Speaker Driver Playback Volume'

root@am57xx-evm:~# amixer cget numid=1
numid=1,iface=MIXER,name='Speaker Driver Playback Volume'
; type=INTEGER,access=rw---R--,values=1,min=0,max=31,step=0
: values=0
| dBscale-min=-7.00dB,step=1.00dB,mute=0

root@am57xx-evm:~# amixer cset numid=1 50%
numid=1,iface=MIXER,name='Speaker Driver Playback Volume'
; type=INTEGER,access=rw---R--,values=1,min=0,max=31,step=0
: values=16
| dBscale-min=-7.00dB,step=1.00dB,mute=0

root@am57xx-evm:~# aplay /usr/bin/bass.wav
Playing WAVE '/usr/bin/bass.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

root@am57xx-evm:~# aplay /usr/bin/ooh.wav
Playing WAVE '/usr/bin/ooh.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

Please help us to solve our issue.

Thanks & Best Regards;
Nikunj Patel

  • Hi Nikunj,

    Do you know if there is no output all? Or is there sound but is not correct?
    Could you please share some captures of the related signals? Like speaker outputs, BCLK, WCLK and DIN. I would like to verify if the outputs are enabled and switching, and also verify the clock signal frequencies.
    Could you please share the clock frequencies as well as the sampling frequency? It would be best to know the actual values that are being sent to the device for configuration.
    Have you verified your commands by reading back the registers from TAS2553?
    I can help you with the TAS2553 configuration by its registers based on the application, although I cannot support the driver commands. The TAS2552 driver is provided as an example and tool, but I cannot support it.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    Hi Ivan;

    Thanks for your quick reply.

    Do you know if there is no output all? Or is there sound but is not correct?

    Ans: We got sound but does not proper.

    Please find the below signals:

    1) MCLK

    2) WCLK: (Frequency : 92.165 Khz)

    3) BITCLK [Frequency: 2.90 Mhz]

    4) Signal at speaker (-Ve) terminal




    Could you please share the clock frequencies as well as the sampling frequency?

    Ans: clock frequency means MCLK so we give it 12 Mhz. Also we are not passing any sampling frequency in our configuration.

    Have you verified your commands by reading back the registers from TAS2553?

    Ans: No

    Also tell who can help us for the Linux driver support for TAS2553 Codec IC?



    Thanks & Best Regards;
    Nikunj Patel

  • In reply to Nikunj Patel:

    Nikunj,

    Sampling frequency for TAS2553 should match with WCLK frequency. This is explained in datasheet section 7.3.7 on page 16. It is usually 44.1kHz or 48kHz.
    Also as WCLK is 1 bit long so the device must be configured for DSP mode (more details on datasheet page 25).
    Usually BCLK and WCLK are multiples (related in frequency) e.g. for WCLK = 48kHz and 32bit data, BCLK should be 3.072MHz (48kHz*32bit*2channel). Is BCLK supposed to be 32 times WCLK frequency?

    The device should be configured to work properly.
    - Clock tree as explained in section 7.3.7. Related registers: 0x01, 0x08, 0x09, 0x0a
    - Data format as explained in section 7.4.1. Related registers: 0x03, 0x05
    - Device configuration as explained in section 7.5.4, register 0x02

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    Hi Ivan;

    We are giving the sampling frequency(44.1kHz or 48kHz.) which is manage by the aplay Application.

    Is BCLK supposed to be 32 times WCLK frequency?

    Ans: As per our manual measuring the BCLK=2.90 MHz and WCLK=92.165 KHz and as per those BCLK is 32 times to the WCLK. (92.165 Khz x 32 = 2.94928 Mhz)

    So, Please tell us where we are wrong?


    Can TAS2553 is compatible with internal OC? because I have enable the internal OC by the below method but still audio is not correct.

    pll_clkin = 1800000;

    pll_sel = (TAS2552_PLL_CLKIN_1_8_FIXED << 3) & TAS2552_PLL_SRC_MASK;

    snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_PLL_SRC_MASK,pll_sel);

    Thanks & Best regards;

    Nikunj Patel

  • In reply to Nikunj Patel:

    Gentle reminder;

    Thanks & Best Regards;
    Nikunj Patel
  • In reply to Nikunj Patel:

    Nikunj,

    If you're giving 44.1kHz or 48kHz by aplay command, then WCLK signal should be 48kHz, not 92.165kHz.
    I would start looking at that to obtain correct signals from the host.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    HI Ivan;
    can you suggest me the next steps for more debugging for above issue?

    Thanks & Best Regards;
    Nikunj Patel
  • In reply to Nikunj Patel:

    Hi Ivan;
    I have read all the registers of TAS2553 IC. please check the below value of each registers

    [ 2065.141544] TAS2552_DEVICE_STATUS =0x00
    [ 2065.149087] TAS2552_CFG_1 =0x36
    [ 2065.156089] TAS2552_CFG_2 =0x6d
    [ 2065.162707] TAS2552_CFG_3 =0x5d
    [ 2065.168523] TAS2552_DOUT =0x00
    [ 2065.175402] TAS2552_SER_CTRL_1 =0xc4
    [ 2065.182972] TAS2552_SER_CTRL_2 =0x00
    [ 2065.189736] TAS2552_OUTPUT_DATA =0xc8
    [ 2065.197733] TAS2552_PLL_CTRL_1 =0x19
    [ 2065.205240] TAS2552_PLL_CTRL_2 =0x03
    [ 2065.212678] TAS2552_PLL_CTRL_3 =0x6f
    [ 2065.219696] TAS2552_BTIP =0x8f
    [ 2065.226314] TAS2552_BTS_CTRL =0x80
    [ 2065.233463] TAS2552_RESERVED_0D =0xbe
    [ 2065.240566] TAS2552_LIMIT_RATE_HYS =0x08
    [ 2065.249108] TAS2552_LIMIT_RELEASE =0x04
    [ 2065.257149] TAS2552_LIMIT_INT_COUNT =0x00
    [ 2065.265606] TAS2552_PDM_CFG =0x01
    [ 2065.272442] TAS2552_PGA_GAIN =0x10
    [ 2065.279033] TAS2552_EDGE_RATE_CTRL =0x40
    [ 2065.287557] TAS2552_BOOST_APT_CTRL =0x0f
    [ 2065.295669] TAS2552_VER_NUM =0x08
    [ 2065.302443] TAS2552_VBAT_DATA =0x00

    So please check that and tell us is there any wrong happen to there. because i have doubts on "TAS2552_SER_CTRL_1", "TAS2552_CFG_1" resistors.

    Thanks & Best Regards;
    Nikunj Patel
  • In reply to Nikunj Patel:

    Hi Nikunj,

    The settings for the mentioned registers does not seem to be correct.
    CFG_1 (register 0x01) is selecting internal 1.8-MHz oscillator as source for PLL, that can be correct, but it also sets Class-D to Mute and sets the device into Software Shutdown mode. That is not correct.
    SER_CTRL_1 (register 0x05) sets BCLK and WCLK as output, so the device is set as Master for digital interface, and the data format is set to DSP. Both things are not correct. This register value explains why WCLK is 1-bit long (DSP format).

    Do you know how is the device being initialized? Perhaps if you can edit the initialization to the correct values the audio will be good.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators
  • In reply to Ivan Salazar:

    Hi Ivan;
    Thanks for your quick reply.
    Sorry for inconvenience. I am out of office for two days so I will check another setting and reply back after two days.

    Thanks & Best regards;
    Nikunj Patel

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