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ADC128S102: Failure Mode Scenario

Sean McCarthy
Prodigy 160 points
Part Number: ADC128S102

Hello,

I have a design using these 2 ADC converter with a shared SPI interface.  The SPI originate at my board level thru LVDS line interface (SN65LVDS32DR Receiver & SN65LVDS31MDREP Driver).  To conserve connector interface pins I have a single chip select (CS) on LVDS side, wired to 2 LVDS line receiver but which are crossed from each other to offer 2 CS that are inverted from each other.  In this way one of the 2 ADC is always selected

The failure scenario I am considering is in regard to LVDS line receiver where I could have unpredictable CS level.  This could be the case if LVDS differential input  follows the case of -100-mV < Vid < +100-mV.

In such case the CS outputs from the LVDS line receiver could both be at a low state.  In such case is there any possibility that the 2 ADC's , with their MISO lines tied together could pose a damaging scenario to the ADC ?  I am thinking that one MISO line could be transmitting a high level while the other a low level and cause an uncontrolled short circuit current between the two?

Regards,

Sean

  • 0
    TI__Mastermind 25020 points

    Hello Sean,

    You are correct, if both devices have active digital buses at the same time, and have shared lines, the device can result in unpredicted failure modes. 

    While the devices are driving the SDO at different states, there can be an unlimited current flowing through the devices, which could cause damage. 

    I would suggest adding a mitigation methods where the devices do not have active buses simultaneously, only one CS asserted at a time

    Regards

    Cynthia 

  • 0
    Prodigy 160 points

    Hello Cynthia,

    Thank you for confirming my understanding of this failure scenario.  Another option for mitigation may consider external current limiting...which seems the most feasible at this late stage of design.

    The ADC absolute max rating indicates 10-mA on any one pin.  But this is likely considering the limitation of the ESD protection diodes.  In my case the ESD diodes are not the issue but rather the ADC MISO output drive stage. In such case its not clear what may be tolerable here ?  Are you able to offer any further guidance on what may be considered for a protection current target ?

    Regards,

    Sean

  • +1 in reply to Sean McCarthy
    TI__Mastermind 25020 points

    The 10mA limit applies to any individual pin of the device,

    When the analog input may exceed the supply voltage, we suggest limiting the current to 2mA.

    Given that this is a digital output and can source 200uA and sink 1mA, I suggest to use a value within this range to define the limiting current. 

    Regards

    Cynthia