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Original question:

DAC5674: can dac will take signed sample data

DAC5674: Output DAC

Roja Veereddy
Intellectual 320 points

Part Number: DAC5674

Hi

I have tried some scenarios with DAC5674

1. External clock given to DAC is 100MHZ , need to get output is 30MHZ. I have given same in the DDS compiler also. but the output is coming 10MHZ only.

2. External clock given to DAC is 200MHZ , need to get output is 30MHZ. I have given same in the DDS compiler also. but the output is coming 20MHZ only.

3. External clock given to DAC is 180MHZ , need to get output is 30MHZ. I have given same in the DDS compiler also. but the output is coming 15MHZ only.

4.External clock given to DAC is 400MHZ , need to get output is 30MHZ. I have given same in the DDS compiler also. but the output is coming 30MHZ.

We unable to understand this scenario, please suggest us to resolve this issue.

Thanks

Roja V

  • 0
    TI__Mastermind 45670 points

    Hi Roja,

    Are you using your own board design or is the problem with the evaluation board from TI?

    Please advise.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Intellectual 320 points

    Hi

    We are using our own design, but the schematic which we used same as Ti.

    Please suggest us to resolve.

    Thanks

    Roja V

  • 0 in reply to Roja Veereddy
    TI__Guru* 91947 points

    Roja,

    What are the settings for DIV0, DIV1, X4, HP1, and HP2? Are you trying to use the internal PLL or not? What is the data rate coming into the DAC? What do you mean by DDS compiler? If using the device in external clock mode, what is the frequency of the signal on the PLLLOCK pin? Can you send your test pattern file that is creating this 30MHz tone?

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 320 points

    Hi

    We are using external clock mode with 200MHZ frequency from signal generator. We are using x4 configuration so that DIV0 and DIV1 is "XX", "XX", HP1 and HP2 is given to 0s that  means we are using low pass and low pass .

    PLL LOCK is coming 50MHZ, i am thinking that x4 configuration with external clock mode so that 200/4=50MHZ(PLL LOCK).

    Pleae can you help me about this.

    Thanks

    Roja V

  • 0 in reply to Roja Veereddy
    TI__Guru* 91947 points

    Roja,

    With the PLLLOCK at 50MHz, the data rate coming into the DAC must be 50MHz and synchronized to this clock. The input data must meet setup and hold times per figure 27 of the data sheet. Are you using the PLLLOCK to clock your data? With the data rate at 50MHZ and using 4x interpolation, the max output frequency you can achieve is Fdata * 0.4 = 50MHz * 0.4 = 20MHz. This may be your issue. You cannot get 30MHz output using a 200MHz clock.

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 320 points

    Hi

    If we change x4 to 2x mode, can we get 200MHZ to 30MHZ.

    I need to send data samples to dac with respect to PLLLOCK or DAc external clock.

    Please help to resolve

    Thanks

    Roja

  • +1 in reply to Roja Veereddy
    TI__Guru* 91947 points

    Roja,

    You should be able to get 30MHz using a 200MHz clock with 2x mode. You could use either clock to sample DAC data samples as they are synchronized. The external clock would have to be divided down though as it will be running 2 times faster than the data rate. Again, the sample data must meet setup and hold time with respect to PLLLOCK clock. I would strongly suggest you use PLLLOCK though for this.

    Regards,

    Jim