DAC8812: POR issue

Hi Hiroshi,

Is DAC OUT updated with LDAC = Low even if the number of clocks is 18 bits or less? (In this case, when CS = Hi) --- No, DAC requires min 18 bits. If more than 18bits are present along with SCLK, last 18bits will be considered.

Now coming back to RS, how RS is driven? Through /CS and RC circuit? Can you draw the same?

What is the state of MSB pin? Is it high or low?

What is happening if you directly connect /RS pin to logic low?

Regards,

AK

Hi Akhilesh K-san,

Thank you for your quick response.

When RS = Low, the output of I-V AMP remains 0V.
This is the customer intended. Since it is fixed at MSB = Low (sorry, I missed mentioning "MSB" in the previous post).

// This is R and C connected to RS.

When the reset rise slope is slowed down, the OUTPUT of I-V AMP is 0V (normal).

After first POR,
/ VOUTA is -4.2V
/ VOUTB is 0V

It works for only 1 second and turns off. It will turn on again after 1 second.
After the second POR, both VOUTA and B will be -4.2V...

It is driven intermittently on the system for 1 second and may not turn off completely.

I/V AMP is a buffer without external resistors.
The circuit diagram is not attached because the customer's consent is required, but it is the same simple circuit.

Best Regards,

Hiroshi

Hi Akhilesh K-san,

We received the schematic and measurement results from our customer.

They removed the RS CAP, but the result is the same.

First turn-on: only VOUT_A shifts from 0V to -4.4V.

Second turn-on: Both VOUT_A and B shifts from 0V to -4.4V.

The power supply of OPAMP is +/- 15V.

5V and 3.3V are made from a 15V power supply.

And the 15V power supply uses an external regulated power supply, and the power on / off cycle is controlled by an external device.

That is, the power is on / off at the board level, so the microcontroller is not running while the power is off.

 Also, the SPI is connected to a microcontroller, but no signal is input or output in this test.

I don't understand why the situation is different between the first and second turn-ons.

I think there is a possibility of failure due to some leak current.

 Please let me know if there is a problem with this circuit, power on / off cycle and this circuit.

//Previous circuit (RS: 10k ohm, 0.01uF)

* File:DAC8812 POR.xlsx

//Change RS circuit

I apologize for the inconvenience.
Please give me some advice.

Best Regards,
Hiroshi

Hi,

Can I get following waveforms as well?

+/-15V ramp, 3.3V, VOUT_A and B with RS pulled high to 3.3V

Regards,

AK

Hi,
Thank you for your support.
Attach additional measurement results.
I would appreciate it if you could check it.

Best Regards,

Hiroshi

Hi Hiroshi-san,

I am concerned that this very long ramp time for the RS pin is causing the device to enter in an unexpected POR state.  Can the MCU keep these pins low until it is the fully powered? Or you can connect RS to VDD (+5V) as that seems to have a faster ramp.

Thanks,

Paul

Hi Paul-san,

As you pointed out, it seems to be malfunctioning during the RS long ramp.
I'm sorry I didn't notice.

At first, the customer had no problem when increasing the RS time constant value because the RS Low time was long.

I will request the following retest.
・ Keep RS low until 3.3V (5V) rises by logic control.

Best Regards,

Hiroshi

Hi Hiroshi-san,

Please let us know when the customer completes the retest. Due to the holiday weekend in the US our response may be delayed until Wednesday June 2nd.

Best,

Katlynne Jones

Hi, all,

When RS is pulled up at 5V
After RS starts first, CS slowly reaches 3.3V (malfunction occurs during that time)

Therefore, I think that the cause is not the reset trouble but the operation due to the intermediate voltage of the logic level.

The 74xxx series logic ICs have a regulation of "Δt / Δv (Input transition rise or fall rate)".

Does the DAC8812 need this consideration?
Please let us know what you think.

Customers are worried that setting RS low enough time will not solve this problem.

Best regards,

Hiroshi

I would not expect the CS line to cause this problem.  My expectation is that the lack of RS control is  causing this issue.

Thanks,

Paul

Hi Paul,

I asked the customer for additional research on CS Line.
First, this is an existing circuit. Vout B works unintentionally during RS or CS ramps.

Next, if you remove the CS pull-up, CS will start up later than the RS ramp-up. At this time, the firmware controls only VoutA.
So VoutA is correct and VoutB is unintended output.

From this, I think this issue depends on CS as well as RS.

I think the only safe way is to hold RS low until CS is HI. Is this correct at the IC design level? Or TI experience is OK.
The customer has not yet tested this method (difficult because the microcontroller does not control the RS).

This may be common sense, but I've never seen the same trouble with this mature DAC.

If there is no guarantee, the customer may start evaluating the AD5455.

We want to avoid re-evaluation of ADI products.
They have been desperate for a few years of replacement since they were kicked out.

Unless there is some TI guarantee, my judgment is meaningless.

I believe TI's excellent support will lead to continued customer use.

Best regards,
Hiroshi

Hi Hiroshi-san,

We are working with our design team to see if we can get some clarity on this.

Thanks,

Paul