ADS1282-HT: Fdata meaning

Hi Jay Prizant,

"Fdata" refers to the output data rate.

Keep in mind that the ADS1282-HT is an oversampling ADC, so the input sampling rate and output data rate are related by an oversampling ratio (OSR), determined by the FILTER[2:0] and DR[2:0] register fields. If you are providing the nominal Fclk to the device of 4.096 MHz and using the FIR filter, then Fdata will correspond to the FIR Data Rates shown in Table 6. For the SINC filter data rates, refer to Table 5. If Fclk is not equal to 4.096 MHz, then Fdata willbe scaled by a factor of (Fclk / 4.096MHz).

The purpose of Figure 42 and Figure 43 is to show the group-delay for a step input when continuously converting (so ignoring the latency of the first conversion result).

However, "Tdr" refers to the digital filter settling time when beginning a new conversion (for example after giving a SYNC command or when changing the MUX inputs). Whenever you begin a new conversion, the digital filter taps will reset and the first conversion result will be delayed until the filter has settled. The settling time for the FIR filter is approximately 63 conversion periods (or 63/Fdata). The /DRDY signal will not go low until the digital filter has settled. However, after the first /DRDY falling edge you will start to see /DRDY falling edges occur at the expected output data rate. If a step-input change occurs after this first conversion result, then the filter output waveform will take the shape of figure 42.

Best regards,
Chris

In the section on Calibration Commands, it talks about "64 data periods later", and "after 16 data periods". Are these data periods referring to the output sample rate? So if it is 4000 sps, then a data period is 1/4000 seconds? Thanks. 

In figure 61, what happens if this sequence is interrupted by other commands? For example, if after the sync or RDATAC at the beginning,  a different cmd is received, does the sequence have to start over? What happens to drdyn if it has gone high? Also it shows the 64 data periods starting after sync. What happens if the 64 data periods elapse before the rdatac is received? Does drdyn wait to go low until a rdatac is received? Thanks. 

Hi Jay Prizant,

To answer your questions...

Jay Prizant said:

In figure 61, what happens if this sequence is interrupted by other commands? For example, if after the sync or RDATAC at the beginning,  a different cmd is received, does the sequence have to start over?

I suppose it would depend on the specific command... I don't think reading conversion data or reading a register would require you to restart this command sequence (although, register reads require the device to be in SDATAC mode). However, writing to a device register or issuing a SYNC or RESET command would cause the digital filter to reset, so sending these commands before the calibration command would require you to restart the whole sequence.

During calibration (the 16 data periods) I'd say you'd shouldn't be sending any SPI commands during this time. Generally you'd want the digital interface to be "quiet" during this time to avoid any digital noise from affecting the calibration. If you have a good PCB layout then this probably isn't an issue though (see [FAQ] PCB Layout Guidelines and Grounding Recommendations for High-Resolution ADCs).
 

Jay Prizant said:

What happens to drdyn if it has gone high?

Unless you clock out data after the 64 data periods, /DRDY will probably remain low. Let say you read the data and then issue the SDATAC, OFSCAL, and RDATAC commands...in this case /DRDY would remain high, but the device would still begin converting.

However, what I  am not sure about is if /DRDY will remain high until the 16 conversion periods have completed, or if will pulse high after each conversion (requiring you to count 16 /DRDY falling edges). I will test this behavior and get back to you.
 

Jay Prizant said:

Also it shows the 64 data periods starting after sync. What happens if the 64 data periods elapse before the rdatac is received? Does drdyn wait to go low until a rdatac is received?

If I recall correctly, I think the RDATAC commands are there simply to enable the /DRDY pin. If you do not send either RDATAC byte then /DRDY would likely stay HIGH (but the device would still be performing data conversions). If you sent the RDATAC command after the 64 data periods, then /DRDY should go low after the next conversation completes. Depending on the output data rate, 64 conversion periods may be on the order of 64 ms (@1kSPS), which should allow more than enough time for the SPI controller to issue the RDATAC command before this time elapses.

And while we're on the topic of RDATAC/SDATAC, I am not certain if the SDATAC command is strictly required or not in the calibration sequence... Figure 61 seems to imply that the device needs to be in SDATAC mode before you can send the SYNC or calibration commands. However, I believe SDATAC mode is only required when you want the DOUT pin to clock out something other than conversion data (i.e. when reading a register value). I'll try and run this sequence without the SDATAC command and let you know if it is needed or not.
 

Best regards,
Chris

If it is in pulse sync mode, and a sync command is given, Figure 46 shows drdyn stays high for Tdr, which in fir mode is 63 data periods + 466 clk cycles. In sinc filter mode it is something else. How does it know the sync command is not as I just described, or the beginning of a Cal command sequence? Although in FIR filter mode, 63 data periods + 466 clk periods is close to 64 data periods. But in Sinc filter mode, it is not close. 

After a CAL command, drdyn goes high for 16 data periods, then the falling edge of drdyn signifies cal is complete. Then what?, what causes drdyn to go back high for normal read continuous operation?