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ADS1115: I2C reading 0xFFFF when reading non blocking

Cristobal Puertas
Prodigy 10 points
Part Number: ADS1115

Hi all

the ADS1115 I2C gives no values from Channel (Register 0) back if the read process is interrupted for longer than 30 ms.

I'm working with linux and sometimes during the read of the two bytes, after reading the first byte, the processor stops reading and continues the read of the second byte with a delay.

In cases where the read delay between first and second byte read is bigger than ~30ms, the master reads 0xFFFF.

By analyzing the SDA bus with an logic analyzer, I can see after reading the first byte, is SDA still low for period (<20 ms) und than it's released to high.

After this case the master read the second byte and receive 0xFFFF. 

Important: The master does not clock during the delay, so nothing happens on the bus, till master want's to read again.

So my question is, if the ADS1115 has some timeout restrictions? 

Has anybody have same or similar issues during the read process of this IC?

Thanks in advance.

  • 0
    TI__Mastermind 31655 points

    Hello Cristobal,

    I don't know if there is some kind of timeout built in to the ADS1115, but I can look into that. To avoid this are you able to do 2 separate single-byte reads to retrieve the data from the register instead of a single two-byte read?

    Regards,

  • 0
    Prodigy 10 points

    Hi Scott

    thank for your reply. Either I can't do two single byte read from the application, then the kernel of linux does only give ACK when he knows, that multiple byte read is needed. I mean, if I tell to read one byte, then the kernel does NACK and when I read two bytes, then after first byte we do ACK and at the end of reading the second byte NACK.

    Of course if I modify the kernel, on that way that I can tell him always do ACK, but it's not an option, cause it would impact to the application to other I2C drivers.

    What I could see is also, this issue does happen only when I read the Register 0x00 (Data). If I read the config register 0x01, with delay between the first and second byte, then it works fine. So one of my question is, could it be that SOC will get interrupted caused of the ADC sampling, when the new value is avaiable?

    Best Regards

  • 0 in reply to Cristobal Puertas
    TI__Mastermind 31655 points

    Hi Cristobal,

    Yes, it is possible this is a result of the measurement updating. One way to test this would be to do a single-shot measurement and see if you are able to read the two bytes with a delay between them. Depending on the requirements of your application, it may actually be better to perform single-shot measurements as opposed to a continuous output. The main disadvantage is that there is a small startup time for each single-shot measurement, but if you do not require a high frequency output, using the single-shot mode can simplify things from a timing perspective.


    Regards,

    Scott