Other Parts Discussed in Thread: TSC2046
Hi Sir,
For parameters of TSC2046E,
Is the built-in reference voltage enabled at power up?
DCLK is low at the time of CS falling, is it okay if it is high?
Waiting your clarification.
Thanks.
Regards,
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Hi Frank,
The reference in the TSC2046E is controlled by the command byte, bit PD1 specifically. Each conversion cycle needs a command byte so the internal reference functionality is controlled on a cycle-by-cycle basis. The interface on the TSC2046 is an SPI type with mode 0, where clock phase and polarity are both 0.
Hi Tom,
Thank you.
For Built in reference on / off
I know that it is set by PD1,
but is the initial state set before setting? Or off? Or is it indefinite?
In addition,we know that the DCLK level at CS fall is low.
Another device is connected to the SPI line in my design.
The DCLK level when CS falls is high.
If high or normal,
I want to use it without changing it, but
Is it not working normally?
Thanks for your clarification.
Hi Frank,
There is no defined power on or 'reset' state for the TSC2046E, but my assumption is that the defaults would be 0x00. I do not have any detail to share if you were to use a different clock polarity setting. You say "it is not working normally" if DCLK is high when CS falls, so you should retain the original settings.
Hi Tom,
Thank you.
we wanna use TSC2046E in my design.
We are considering using "differential reference mode (SER/ DFR low)".
can you tell me recommended unused pin handling method?
Vbat = GND?
Aux = GND?
Busy = open?
VREF = pull Up or pull Down?
Thanks.
Regards,
Hi Frank,
If you have the space, place a 10K to ground on the Vbat and Aux inputs. Add a footprint for a capacitor to ground on Vref. BUSY can be left open although its handy for troubleshooting/debug purposes, so I'd at least add a test/probe point there.