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ADS127L01: Synchronizing two ADCs, deterministic timing

Ue
Genius 17445 points

Part Number: ADS127L01

Hi all

My customer is using two ADS127L01 in a network analyzer frontend with an input frequency of maximum 200kHz.

As they are looking for lowest possible phase error between the two channels they need deterministic timing / synchronization for the two ADC127L01 (f_CLK = 16MHz, OSR = 32, f_DATA = 500ks/s).

The START pin of both ADCs are connected and the start signal goes from low to high at the falling edge of the common CLK.

With this set up they expect the ADCs to be perfectly synchronized.

At 16MHz f_CLK e t_SU = 31.25ns, well above the minimum value of 10ns.

Therefore the two  #DRDY signals should change from high to low simultaneously, meaning data is available at the same time.

Looking at the datasheet and the timing for #DRDY going from high to low they find only a typical value.

They expect the ADCs to perform exactly the same, if this isn't the case they have a problem with this concept.

Can you confirm the two ADCs are always synchronized the same way ?

Thank you and best regards

Ueli

  • +1
    TI__Guru 51650 points

    Hello Ueli,

    As long as the t_SU is met, 10nS or greater, then the separate ADC's will be synchronized to the exact same clock edge.  However, there will be differences in the exact timing to the nanosecond level due to small differences in board routing of CLK and START signals. 

    The delay time td-NDR is specified as 'typical' but it is an exact number of CLK cycles and depends on the filter setting.  As long as all ADC's have the same filter and OSR settings, the number of CLK cycles for td-NDR will be exactly the same for all ADC's.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • +1 in reply to Keith Nicholas
    TI__Genius 17445 points

    Hello Keith

    Thank you for the quick reply and for the clarification, that's good news.

    Best regards

    Ueli