Hi team,
Here is the inquires from customer.
- They would like to use 3.3V at DVDD to communicate with FPGA I/O. Are there any concern if DVDD is a little bit over 3.3V ?
- In case of CLK input (master clock) at 20MHz and SCLK_SEL=’0’, SCLK is same as CLK input at 20MHz even if both /LVDS=’0’ and ‘1’.
Referring the datasheet, SCLK should be same with CLK input (master clock)
(Background)
They will use 625ksps sampling rate and would like to know the interface should be LVDS or CMOS. (The length between FPGA and ADS1672 is several 10mm) - According to datasheet, the clock amplitude should be equal to AVDD. It means that 5V amplitude clock source driving AVDD at 5V is needed ?
Thank you and best regards,
Michiaki